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AgeCommit message (Expand)AuthorFilesLines
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2-24/+43
2020-06-30RISC-V: Cleanup the include/opcode/riscv-opc.h.Nelson Chu1-33/+26
2020-06-22aarch64: Normalize and sort feature bit macrosAlex Coplan1-64/+47
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-4/+0
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2-219/+217
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan1-0/+4
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi1-2/+2
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi1-1/+8
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu1-3/+2
2020-05-28PR26044, Some targets can't be compiled with GCC 10 (tilepro)Alan Modra1-3/+1
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu2-261/+324
2020-05-19Fix the ARM assembler to generate a Realtime profile for armv8-r.Alexander Fedotov1-1/+2
2020-05-11Power10 Reduced precision outer product operationsAlan Modra1-13/+16
2020-05-11PowerPC Rename powerxx to power10Alan Modra1-2/+2
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+1
2020-03-30RISC-V: Update CSR to privileged spec 1.11.Nelson Chu1-6/+19
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-244/+244
2020-02-10[binutils][arm] arm support for ARMv8.m Custom Datapath ExtensionMatthew Malcomson1-0/+9
2020-02-04ubsan: d30v: negation of -2147483648Alan Modra1-1/+1
2020-01-16[binutils][arm] PR25376 Change MVE into a CORE_HIGH featureAndre Vieira1-4/+3
2020-01-15MSP430: Fix relocation overflow when using #lo(EXP) macroJozef Lawrynowicz1-0/+15
2020-01-13tic4x: sign extension using shiftsAlan Modra1-5/+7
2020-01-10ubsan: spu: left shift of negative valueAlan Modra1-17/+20
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi1-0/+2
2020-01-02Enable building the s12z target on Solaris hosts where REG_Y is defined in sy...Nick Clifton1-10/+14
2020-01-01Update year range in copyright notice of binutils filesAlan Modra68-68/+68
2019-12-17Remove tic80 supportAlan Modra1-283/+0
2019-12-16ubsan: crx: left shift cannot be represented in type 'int'Alan Modra1-1/+1
2019-12-16ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra1-3/+4
2019-12-11bfd signed overflow fixesAlan Modra1-8/+8
2019-12-11ubsan: left shift of cannot be represented in type 'int'Alan Modra1-18/+18
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-1/+3
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-16/+16
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-0/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-1/+9
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-0/+6
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-5/+10
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-1/+3
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-3/+20
2019-08-30[ARC] [COMMITTED] Fix FASTMATH field.Claudiu Zissulescu1-1/+1
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ...Yoshinori Sato1-47/+47
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu1-0/+2
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+1
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-1/+1
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner1-0/+18
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira1-0/+2
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+1
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