| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 1 | -0/+6 |
| 2023-07-24 | bpf: add support for jal/gotol jump instruction with 32-bit target | Jose E. Marchesi | 1 | -1/+2 |
| 2023-07-21 | bpf: opcodes, gas: support for signed load V4 instructions | Jose E. Marchesi | 1 | -0/+3 |
| 2023-07-21 | bpf: opcodes, gas: support for signed register move V4 instructions | Jose E. Marchesi | 1 | -0/+5 |
| 2023-07-21 | DesCGENization of the BPF binutils port | Jose E. Marchesi | 1 | -0/+306 |
| 2023-07-18 | RISC-V: Supports Zcb extension. | Jiawei | 2 | -0/+52 |
| 2023-07-03 | RISC-V: Zvkh[a,b]: Remove individual instruction class | Christoph Müllner | 1 | -2/+0 |
| 2023-07-01 | RISC-V: Add support for the Zvksh ISA extension | Christoph Müllner | 2 | -0/+9 |
| 2023-07-01 | RISC-V: Add support for the Zvksed ISA extension | Christoph Müllner | 2 | -0/+12 |
| 2023-07-01 | RISC-V: Add support for the Zvknh[a,b] ISA extensions | Christoph Müllner | 2 | -0/+14 |
| 2023-07-01 | RISC-V: Add support for the Zvkned ISA extension | Christoph Müllner | 2 | -0/+36 |
| 2023-07-01 | RISC-V: Add support for the Zvkg ISA extension | Christoph Müllner | 2 | -0/+9 |
| 2023-07-01 | RISC-V: Add support for the Zvbc extension | Nathan Huckleberry | 2 | -0/+15 |
| 2023-07-01 | RISC-V: Add support for the Zvbb ISA extension | Christoph Müllner | 2 | -0/+55 |
| 2023-06-30 | RISC-V: Add support for the Zfa extension | Christoph Müllner | 2 | -0/+105 |
| 2023-06-30 | LoongArch: gas: Add LVZ and LBT instructions support | mengqinggang | 1 | -0/+6 |
| 2023-06-30 | LoongArch: Deprecate $v[01], $fv[01] and $x names per spec | WANG Xuerui | 1 | -2/+2 |
| 2023-06-30 | opcodes/loongarch: remove unused code | WANG Xuerui | 1 | -5/+0 |
| 2023-06-30 | LoongArch: support disassembling certain pseudo-instructions | WANG Xuerui | 1 | -0/+2 |
| 2023-06-27 | RISC-V: Support Zicond extension | Philipp Tomsich | 2 | -0/+9 |
| 2023-06-25 | LoongArch: Support referring to FCSRs as $fcsrX | Feiyang Chen | 1 | -0/+2 |
| 2023-06-15 | Add MIPS Allegrex CPU as a MIPS2-based CPU | David Guillen Fandos | 1 | -0/+6 |
| 2023-06-15 | Revert "MIPS: add MT ASE support for micromips32" | Maciej W. Rozycki | 1 | -25/+10 |
| 2023-06-15 | Revert "MIPS: sync oprand char usage between mips and micromips" | Maciej W. Rozycki | 1 | -12/+2 |
| 2023-06-05 | MIPS: sync oprand char usage between mips and micromips | YunQiang Su | 1 | -2/+12 |
| 2023-06-05 | MIPS: add MT ASE support for micromips32 | YunQiang Su | 1 | -10/+25 |
| 2023-06-01 | RISC-V: PR30449, Add lga assembler macro support. | Jim Wilson | 1 | -0/+1 |
| 2023-05-30 | LoongArch: include: Add support for linker relaxation. | mengqinggang | 1 | -0/+3 |
| 2023-04-26 | RISC-V: Support XVentanaCondOps extension | Philipp Tomsich | 2 | -0/+9 |
| 2023-03-30 | aarch64: Remove stray reglist variable | Richard Sandiford | 1 | -1/+1 |
| 2023-03-30 | aarch64: Add the RPRFM instruction | Richard Sandiford | 1 | -0/+2 |
| 2023-03-30 | aarch64: Add new SVE dot-product instructions | Richard Sandiford | 1 | -1/+2 |
| 2023-03-30 | aarch64: Add the SME2 shift instructions | Richard Sandiford | 1 | -0/+3 |
| 2023-03-30 | aarch64: Add the SME2 saturating conversion instructions | Richard Sandiford | 1 | -0/+1 |
| 2023-03-30 | aarch64: Add the SME2 MLALL and MLSLL instructions | Richard Sandiford | 1 | -0/+5 |
| 2023-03-30 | aarch64: Add the SME2 MLAL and MLSL instructions | Richard Sandiford | 1 | -0/+4 |
| 2023-03-30 | aarch64: Add the SME2 FMLA and FMLS instructions | Richard Sandiford | 1 | -0/+2 |
| 2023-03-30 | aarch64: Add the SME2 maximum/minimum instructions | Richard Sandiford | 1 | -0/+1 |
| 2023-03-30 | aarch64: Add the SME2 ADD and SUB instructions | Richard Sandiford | 1 | -0/+3 |
| 2023-03-30 | aarch64: Add the SME2 ZT0 instructions | Richard Sandiford | 1 | -0/+11 |
| 2023-03-30 | aarch64: Add the SME2 predicate-related instructions | Richard Sandiford | 1 | -0/+11 |
| 2023-03-30 | aarch64: Add the SME2 multivector LD1 and ST1 instructions | Richard Sandiford | 1 | -0/+3 |
| 2023-03-30 | aarch64: Add the SME2 MOVA instructions | Richard Sandiford | 1 | -0/+10 |
| 2023-03-30 | aarch64: Add support for predicate-as-counter registers | Richard Sandiford | 1 | -0/+5 |
| 2023-03-30 | aarch64; Add support for vector offset ranges | Richard Sandiford | 1 | -4/+19 |
| 2023-03-30 | aarch64: Add support for vgx2 and vgx4 | Richard Sandiford | 1 | -0/+13 |
| 2023-03-30 | aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array | Richard Sandiford | 1 | -3/+3 |
| 2023-03-30 | aarch64: Add +sme2 | Richard Sandiford | 1 | -0/+1 |
| 2023-03-30 | aarch64: Add support for strided register lists | Richard Sandiford | 1 | -12/+26 |
| 2023-03-30 | aarch64: Add a aarch64_cpu_supports_inst_p helper | Richard Sandiford | 1 | -0/+3 |
