| Age | Commit message (Collapse) | Author | Files | Lines |
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The code was checking wrong bit for sign extension. It caused it
to zero-extend instead of sign-extend the immediate value.
2021-03-25 Abid Qadeer <abidh@codesourcery.com>
opcodes/
* nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
immediate in br.n instruction.
gas/
* testsuite/gas/nios2/brn.s: New.
* testsuite/gas/nios2/brn.d: New.
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In match_template() i.tm hasn't been filled yet, so it is necessarily t
which needs checking. This is only a latent issue as no other templates
with the same base_opcode have an extension_opcode of 1.
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For VEX-encoded ones, all three involved vector registers have to be
distinct. For EVEX-encoded ones an actual mask register has to be in use
and zeroing-masking cannot be used (violation of either will #UD).
Additionally both involved vector registers have to be distinct for
EVEX-encoded gathers.
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This combination makes no sense and is documented to cause #UD.
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For INVLPGB the operand count was wrong (besides %edx there's also %ecx
which is an input to the insn). In this case I see little sense in
retaining the bogus 2-operand template. Plus swapping of the operands
wasn't properly suppressed for Intel syntax.
For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates
were specified. These get retained, as the address operand is the only
one really needed to expressed non-default address size, but only for
compatibility reasons. Proper multi-operand insn get introduced and the
testcases get adjusted / extended accordingly.
While at it also drop the redundant definition of __amd64__ - we already
have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
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This is only a partial fix for PR/gas 27419, in that it limits the bad
behavior of accepting mismatched operands to just x32 mode. The full fix
would be to revert commits 27f134698ac5 and b3a3496f83a1, and to address
the issue in gcc instead.
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opcodes/
PR 27647
* ppc-opc.c (XLOCB_MASK): Delete.
(XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
XLBH_MASK.
(powerpc_opcodes): Accept a BH field on all extended forms of
bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
gas/
PR 27647
* testsuite/gas/ppc/a2.d: Update expected output.
* testsuite/gas/ppc/power8.d: Likewise.
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In the majority of cases we can easily determine the length from the
encoding, irrespective of whether a prefix is specified there as well.
We further don't even need to record the value in the table entries, as
it's easy enough to determine it (without any guesswork, unless an insn
with major opcode 00 appeared that requires a 2nd opcode byte to be
specified explicitly) when installing the chosen template for further
processing.
Should an encoding appear which
- has a major opcode byte of 66, F3, or F2,
- requires a 2nd opcode byte to be specified explicitly,
- doesn't have a mandatory prefix
we'd need to convert all templates presently encoding a mandatory prefix
this way to the Prefix_0X<nn> model to eliminate the respective guessing
i386-gen does.
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Just like is already done for legacy encoded insns, record the mandatory
prefix information in the respective opcode modifier field. Do this
without changing the source table, but rather by deriving the values from
their existing source representation.
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This is in preparation of opcode_length going away as a field in the
templates. Identify pseudo prefixes by a base opcode of zero instead:
No real prefix has an opcode of zero. This at the same time allows
dropping a curious special case from i386-gen.
Since most attributes are identical for all pseudo prefixes, take the
opportunity and also template them.
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In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX
encoding templates, renumber the pseudo-enumerators such that their
values can then also be used directly in the respective prefix bit
fields.
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To facilitate a subsequent table parser change, re-order CPU flags and
opcode modifier fields. No functional change intended.
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Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX
base_opcode") used the opcodeprefix field for two distinct purposes. In
preparation of having VEX/XOP/EVEX and non-VEX templates become similar
in the representatioon of both encoding space and opcode prefixes, split
the field to have a separate one holding an insn's opcode space.
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Use the constant rather than literal zero. While at it fold two
conditionals (using the same base opcode and prefix) in load_insn_p().
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Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX
base_opcode") dropped the mandatory prefix bytes from legacy encoded
insn templates, but failed to also adjust affected MPX-specific checks
in two places.
For the expressions to remain halfway readable, introduce local
variables to hold current_templates->start.
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bfd/ChangeLog:
* bfd-in.h (startswith): Add startswith function.
(CONST_STRNEQ): Remove.
* bfd-in2.h (startswith): Regenerate with make headers.
* archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith.
(_bfd_slurp_extended_name_table): Likewise.
* archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise.
* bfd.c (bfd_get_sign_extend_vma): Likewise.
(bfd_convert_section_size): Likewise.
(bfd_convert_section_contents): Likewise.
* coff-stgo32.c (go32exe_create_stub): Likewise.
(go32exe_check_format): Likewise.
* coffcode.h (styp_to_sec_flags): Likewise.
(GNU_DEBUGALTLINK): Likewise.
* coffgen.c (_bfd_coff_section_already_linked): Likewise.
(coff_gc_sweep): Likewise.
(bfd_coff_gc_sections): Likewise.
* cofflink.c (coff_link_add_symbols): Likewise.
(process_embedded_commands): Likewise.
* compress.c (bfd_is_section_compressed_with_header): Likewise.
(bfd_init_section_decompress_status): Likewise.
* dwarf2.c (find_debug_info): Likewise.
(place_sections): Likewise.
* ecoff.c (_bfd_ecoff_slurp_armap): Likewise.
* elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise.
* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
(assign_section_numbers): Likewise.
(elfcore_grok_win32pstatus): Likewise.
* elf32-arm.c (cmse_scan): Likewise.
(elf32_arm_gc_mark_extra_sections): Likewise.
(elf32_arm_size_dynamic_sections): Likewise.
(is_arm_elf_unwind_section_name): Likewise.
* elf32-bfin.c (bfin_size_dynamic_sections): Likewise.
* elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise.
* elf32-cris.c (elf_cris_size_dynamic_sections): Likewise.
* elf32-csky.c (csky_elf_size_dynamic_sections): Likewise.
* elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise.
* elf32-iq2000.c (iq2000_elf_check_relocs): Likewise.
* elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise.
* elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise.
* elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise.
* elf32-metag.c (elf_metag_size_dynamic_sections): Likewise.
* elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise.
* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise.
* elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise.
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
* elf32-s390.c (elf_s390_size_dynamic_sections): Likewise.
* elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise.
* elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise.
* elf32-sh.c (sh_elf_size_dynamic_sections): Likewise.
* elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise.
(elf32_tic6x_size_dynamic_sections): Likewise.
* elf32-vax.c (elf_vax_size_dynamic_sections): Likewise.
* elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise.
(xtensa_is_insntable_section): Likewise.
(xtensa_is_littable_section): Likewise.
(xtensa_is_proptable_section): Likewise.
(xtensa_property_section_name): Likewise.
(xtensa_callback_required_dependence): Likewise.
* elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise.
* elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise.
* elf64-ia64-vms.c (is_unwind_section_name): Likewise.
(get_reloc_section): Likewise.
(elf64_ia64_size_dynamic_sections): Likewise.
(elf64_ia64_object_p): Likewise.
* elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise.
* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
* elf64-s390.c (elf_s390_size_dynamic_sections): Likewise.
* elflink.c (elf_link_add_object_symbols): Likewise.
(_bfd_elf_gc_mark_extra_sections): Likewise.
(bfd_elf_parse_eh_frame_entries): Likewise.
(_bfd_elf_section_already_linked): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise.
* elfnn-ia64.c (is_unwind_section_name): Likewise.
(elfNN_ia64_size_dynamic_sections): Likewise.
(elfNN_ia64_object_p): Likewise.
* elfxx-mips.c (FN_STUB_P): Likewise.
(CALL_STUB_P): Likewise.
(CALL_FP_STUB_P): Likewise.
(_bfd_mips_elf_section_from_shdr): Likewise.
(_bfd_mips_elf_fake_sections): Likewise.
(_bfd_mips_elf_size_dynamic_sections): Likewise.
(_bfd_mips_final_write_processing): Likewise.
(_bfd_mips_elf_final_link): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
* elfxx-x86.c (elf_i386_is_reloc_section): Likewise.
(elf_x86_64_is_reloc_section): Likewise.
* hpux-core.c (thread_section_p): Likewise.
* libcoff.h (bfd_pei_p): Likewise.
* linker.c (REAL): Likewise.
(unwrap_hash_lookup): Likewise.
(_bfd_generic_link_add_one_symbol): Likewise.
* mmo.c (mmo_internal_write_section): Likewise.
* osf-core.c (osf_core_core_file_p): Likewise.
* pef.c (bfd_pef_print_symbol): Likewise.
* pei-x86_64.c (pex64_print_all_pdata_sections): Likewise.
* som.c (som_slurp_symbol_table): Likewise.
(som_slurp_armap): Likewise.
* wasm-module.c (wasm_compute_custom_section_file_position): Likewise.
binutils/ChangeLog:
* dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith.
* emul_aix.c (ar_emul_aix_parse_arg): Likewise.
* objcopy.c (is_mergeable_note_section): Likewise.
* objdump.c (dump_dwarf_section): Likewise.
* prdbg.c (pr_method_type): Likewise.
(pr_class_baseclass): Likewise.
(tg_class_baseclass): Likewise.
* readelf.c (process_lto_symbol_tables): Likewise.
* stabs.c (ULLHIGH): Likewise.
(parse_stab_argtypes): Likewise.
(stab_demangle_function_name): Likewise.
gas/ChangeLog:
* config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith.
(x86_64_section_word): Likewise.
* config/tc-sparc.c (md_parse_option): Likewise.
gdb/ChangeLog:
* arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith.
(_initialize_arm_tdep): Likewise.
ld/ChangeLog:
* emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith.
* emultempl/beos.em: Likewise.
* emultempl/elf.em: Likewise.
* emultempl/pe.em: Likewise.
* emultempl/pep.em: Likewise.
* emultempl/xtensaelf.em: Likewise.
* ldctor.c (ctor_prio): Likewise.
* ldelf.c (ldelf_try_needed): Likewise.
(ldelf_parse_ld_so_conf): Likewise.
(ldelf_after_open): Likewise.
(output_rel_find): Likewise.
(ldelf_place_orphan): Likewise.
* ldfile.c (ldfile_add_library_path): Likewise.
* ldlang.c (lang_add_input_file): Likewise.
* ldmain.c (get_sysroot): Likewise.
(get_emulation): Likewise.
(add_archive_element): Likewise.
* ldwrite.c (unsplittable_name): Likewise.
(clone_section): Likewise.
* lexsup.c (parse_args): Likewise.
* pe-dll.c (is_import): Likewise.
(pe_implied_import_dll): Likewise.
opcodes/ChangeLog:
* aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
* arc-dis.c (parse_option): Likewise.
* arm-dis.c (parse_arm_disassembler_options): Likewise.
* cris-dis.c (print_with_operands): Likewise.
* h8300-dis.c (bfd_h8_disassemble): Likewise.
* i386-dis.c (print_insn): Likewise.
* ia64-gen.c (fetch_insn_class): Likewise.
(parse_resource_users): Likewise.
(in_iclass): Likewise.
(lookup_specifier): Likewise.
(insert_opcode_dependencies): Likewise.
* mips-dis.c (parse_mips_ase_option): Likewise.
(parse_mips_dis_option): Likewise.
* s390-dis.c (disassemble_init_s390): Likewise.
* wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
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I don't know really why we should lose a space before a '/'. Possibly
it would make sense if '/' started a comment, but otherwise no.
* app.c (do_scrub_chars): Don't lose spaces before a slash.
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* config/tc-z8k.c (apply_fix): Handle 7-bit relocations correctly.
Problem found by Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>.
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bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
gas/
* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext.d: Likewise.
include/
* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
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This patch adds few missing system registers to GAS: LORC_EL1,
LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2.
gas/ChangeLog:
2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
* testsuite/gas/aarch64/sysreg-7.d: New test.
* testsuite/gas/aarch64/sysreg-7.s: New test.
opcodes/ChangeLog:
2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
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Add support for TLS in XCOFF. Amongst the things done by this commit:
- Update XCOFF auxialiary header to match new version and allow TLS
sections.
- Add TLS sections (.tdata and .tbss) support in gas and ld.
- Add support for the TLS relocations in gas and ld.
Two different types BFD_RELOC are created for PPC and PPC64 as
the size is a pointer, thus distinct in 32 or 64bit.
The addresses given by ld to .tdata and .tbss is a bit special. In
XCOFF, these addresses are actually offsets from the TLS pointer
computed at runtime. AIX assembly and linker does the same. In
top of that, the .tdata must be before .data (this is mandatory for AIX
loader). Thus, the aix ld script is recomputing "." before .data to restore
its original value. There might be a simpler way, but this one is working.
Optimisation linked to TLS relocations aren't yet implemented.
bfd/
* reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE,
BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD,
BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE,
BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M,
BFD_RELOC_PPC64_TLS_ML): New relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* coff-rs6000.c (xcoff_calculate_relocation): Call
xcoff_reloc_type_tls for TLS relocations.
(xcoff_howto_table): Implement TLS relocations.
(_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations.
(xcoff_reloc_type_tls): New function.
* coff64-rs6000.c (xcoff_calculate_relocation): Likewise.
(xcoff_howto_table): Likewise.
(_bfd_xcoff_reloc_type_lookup): Likewise.
* coffcode.h (sec_to_styp_flags): Handle TLS sections.
(styp_to_sec_flags): Likewise.
(coff_compute_section_file_positions): Avoid file offset
optimisation for .data when the previous section is .tdata.
(coff_write_object_contents): Handle TLS sections.
* coffswap.h (coff_swap_aouthdr_out): Add support for
new fields in aouthdr.
* libxcoff.h (xcoff_reloc_type_tls): Add prototype.
* xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL.
(xcoff_need_ldrel_p): Add cases for TLS relocations.
(xcoff_create_ldrel): Add l_symndx for TLS sections.
gas/
* config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section,
(ppc_xcoff_bss_section, ppc_xcoff_tdata_section,
(ppc_xcoff_tbss_section): New variables.
(ppc_text_subsegment, ppc_text_csects, ppc_data_subgments,
(ppc_data_csects): Removed.
(ppc_xcoff_section_is_initialized, ppc_init_xcoff_section,
ppc_xcoff_parse_cons): New functions.
(md_being): Initialize XCOFF sections.
(ppc_xcoff_suffix): Add support for TLS relocations
(fixup_size, md_apply_fix): Add support for new BFD_RELOC.
(ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS
to .bss section. Handle new XCOFF section variables.
(ppc_comm): Likewise.
(ppc_toc): Likewise.
(ppc_symbol_new_hook): Likewise.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Add tbss support.
* config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define.
(ppc_xcoff_parse_cons): Add prototype.
(struct ppc_xcoff_section): New structure.
ld/
* emultempl/aix.em: Ensure .tdata section is removed
if empty, even with -r flag.
* scripttempl/aix.sc: Handle TLS sections.
* testsuite/ld-powerpc/aix52.exp: Add new tests.
* testsuite/ld-powerpc/aix-tls-reloc-32.d: New test.
* testsuite/ld-powerpc/aix-tls-reloc-64.d: New test.
* testsuite/ld-powerpc/aix-tls-reloc.ex: New test.
* testsuite/ld-powerpc/aix-tls-reloc.s: New test.
* testsuite/ld-powerpc/aix-tls-section-32.d: New test.
* testsuite/ld-powerpc/aix-tls-section-64.d: New test.
* testsuite/ld-powerpc/aix-tls-section.ex: New test.
* testsuite/ld-powerpc/aix-tls-section.s: New test.
include/
* coff/internal.h (struct internal_aouthdr): Add new fields.
* coff/rs6000.h (AOUTHDRÃ): Add new fields.
* coff/rs6k64.h (struct external_filehdr): Likewise.
* coff/xcoff.h (_TDATA), _TBSS): New defines
(RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA,
RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY,
RS6K_AOUTHDR_FORK_COR): New defines.
(XMC_TU): Removed.
(XMC_UL): New define.
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Implement support for largetoc on XCOFF.
R_TOCU and R_TOCL are referenced by the new BFD defines:
BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO.
A new toc storage class is added XMC_TE.
In order to correctly handle R_TOCU, the logic behind
xcoff_reloc_type_toc is changed to compute the whole TOC offset
instead of just the difference between the "link" offset and the
"assembly" offset.
In gas, add a function to transform addis format used by AIX
"addis RT, D(RA)" into the ELF format "addis RT, RA, SI".
bfd/
* reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO):
New relocations.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* coff-rs6000.c (xcoff_calculate_relocation): Call
xcoff_reloc_type_toc for R_TOCU and R_TOCL.
(xcoff_howto_table): Remove src_mask for TOC relocations.
Add R_TOCU and R_TOCL howtos.
(_bfd_xcoff_reloc_type_lookup): Add cases for
BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO.
(xcoff_reloc_type_toc): Compute the whole offset.
Implement R_TOCU and R_TOCL.
* coff64-rs6000.c (xcoff64_calculate_relocation):
Likewise.
(xcoff64_howto_table): Likewise.
(xcoff64_reloc_type_lookup): Likewise.
gas/
* config/tc-ppc.c (ppc_xcoff_suffix): New function.
(MAP, MAP32, MAP64): New macros for XCOFF.
(ppc_xcoff_fixup_addis): New function.
(ppc_is_toc_sym): Handle XMC_TE.
(fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
(md_assemble): Call ppc_xcoff_fixup_addis for XCOFF.
(ppc_change_csect): Handle XMC_TE.
(ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE
storage class.
(ppc_symbol_new_hook): Handle XMC_TE.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Likewise.
(md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
ld/
* scripttempl/aix.sc: Add .te to .data section.
* testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+.
Add aix-largetoc-1 test.
* testsuite/ld-powerpc/aix-largetoc-1-32.d: New test.
* testsuite/ld-powerpc/aix-largetoc-1-64.d: New test.
* testsuite/ld-powerpc/aix-largetoc-1.ex: New test.
* testsuite/ld-powerpc/aix-largetoc-1.s: New test.
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Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for
AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn
handling in line with AVX2's, but the disassembler side was forgotten.
This has the benefit of
- allowing to fold a number of table entries,
- rendering a few #define-s and enumerators unused.
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All encodings not used in this range are (reserved) NOPs. Hence their
decoding should be fully consistent. For this to work the PREFIX_IGNORED
logic needs slightly extending, such that the attribute will also
- have an effect when used inside prefix_table[], yet without always
falling back to using slot 0,
- cause prefixes marked as ignored while decoding through prefix_table[]
to no longer be considered decoded, when encountered in a subsequent
decoding step.
In adjacent code also drop meaningless PREFIX_OPCODE.
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RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified
together, so can share an enum-like field. IsLockable can be inferred
from HLE setting and hence only needs specifying when neither of them
is present.
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Despite SYSEXIT being an Intel-only insn in long mode, its behavior
there is similar to SYSRET's: Depending on REX.W execution continues in
either 64-bit or compatibility mode. Hence distinguishing by suffix is
as necessary here as it is there.
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PR 27411
* config/tc-arm.c (do_t_add_sub): Correct error message.
* testsuite/gas/arm/pr27411.s: New test.
* testsuite/gas/arm/pr27411.d: New test driver.
* testsuite/gas/arm/pr27411.l: Expected error output for new test.
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A number of targets, bfin, rl78, rx, can show odd failures when
bfd/reloc.c changes BFD_RELOC_* enum values, if recompiling over a
build dir with existing objects. The problem is caused by
bfin-parse.o and similar not being recompiled and so using stale
BFD_RELOC_* values. This isn't fixed by making bfin-parse.c depend on
bfd/reloc.c, which isn't necessary anyway. bfin-parse.o should have
been recompiled due to bfd/bfd.h changing when extracted bfd/reloc.c
BFD_RELOC_* values change, but that wasn't happening. The problem is
that automake generates a makefile that loads gas/config/.deps/
dependency file for objects with corresponding sources mentioned in
EXTRA_as_new_SOURCES. Unless we want to mess around generating
explicit dependencies, I think that mean moving some object files to
the build gas/config/. This patch does that, removing some hacks for
m68k-parse.c that should no longer be necessary, and removes some
rules that catered to old bison producing code that triggers compiler
warnings.
PR 23691
* Makefile.am (TARGET_CPU_CFILES): Split off config/xtensa-relax.c..
(TARGET_CPU_HFILES): ..and config/xtensa-relax.h..
(TARGET_EXTRA_FILES): ..to here. Add config/bfin-lex-wrapper.c,
and use alongside TARGET_CPU_CFILES.
(EXTRA_DIST): Update location of generated .c files.
(config/m68k-parse.c): New rule replacing m68k-parse.c rule.
(config/bfin-parse.c, config/rl78-parse.cm config/rx-parse.c),
(config/bfin-lex.c, config/bfin-lex-wrapper.@OBJEXT@): Similarly.
(itbl-lex-wrapper.@OBJEXT@): Simplify to just the needed
dependencies.
(itbl-parse.@OBJEXT@): Delete rule using NO_WERROR.
(itbl-parse.c, itbl-parse.h): Tidy.
* config/bfin-lex-wrapper.c: Include config/bfin-lex.c.
* config/bfin-lex.l: Include config/bfin-parse.h.
* configure.ac (extra_objects): Move object files corresponding
to .y and .l files now in config/ to config/.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
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* config/tc-riscv.c (riscv_ip): Fix compile time warnings about
misleading indentation.
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* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM: Renamed from SBTYPE_IMM.
JTYPE_IMM: Renamed from UJTYPE_IMM.
CITYPE_IMM: Renamed from RVC_IMM.
CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM: Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM: Added for .insn without special encoding.
CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
CLTYPE_IMM: Added for .insn without special encoding.
CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
RVC_SIMM3: Unused and removed.
CBTYPE_IMM: Renamed from RVC_B_IMM.
CJTYPE_IMM: Renamed from RVC_J_IMM.
* Added new operands and removed the unused ones,
C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.
bfd/
PR 27158
* elfnn-riscv.c (perform_relocation): Updated encoding macros.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
gas/
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
gdb/
PR 27158
* riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
(decode_j_type_insn): Likewise.
(decode_cj_type_insn): Likewise.
(decode_b_type_insn): Likewise.
(decode): Likewise.
include/
PR 27158
* opcode/riscv.h: Updated encoding macros.
opcodes/
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
sim/
PR 27158
* riscv/sim-main.c (execute_i): Updated encoding macros.
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Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use. To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.
bfd/
* Makefile.am: Added cpu-riscv.h.
* Makefile.in: Regenerated.
* po/SRC-POTFILES.in: Regenerated.
* cpu-riscv.h: Added to support spec versions controlling.
Also added extern arrays and functions for cpu-riscv.c.
(enum riscv_spec_class): Define all spec classes here uniformly.
(struct riscv_spec): Added for all specs.
(RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
(RISCV_GET_SPEC_NAME): Likewise.
(RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
(RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
(RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
* cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
(riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
(riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
(riscv_priv_specs): Moved below.
(riscv_get_priv_spec_class_from_numbers): Likewise, updated.
(riscv_isa_specs): Moved from include/opcode/riscv.h.
* elfnn-riscv.c: Included cpu-riscv.h.
(riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
* elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
(RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
* elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
* config/tc-riscv.c: Included cpu-riscv.h.
(enum riscv_csr_clas): Moved from include/opcode/riscv.h.
(struct riscv_csr_extra): Likewise.
(struct riscv_ext_version): Likewise.
(ext_version_table): Moved from opcodes/riscv-opc.c.
(default_isa_spec): Updated type to riscv_spec_class.
(default_priv_spec): Likewise.
(riscv_set_default_isa_spec): Updated.
(init_ext_version_hash): Likewise.
(riscv_init_csr_hash): Likewise, also fixed indent.
include/
* opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
* riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
(default_priv_spec): Updated type to riscv_spec_class.
(parse_riscv_dis_option): Updated.
* riscv-opc.c: Moved stuff and make the file tidy.
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* testsuite/gas/elf/section28.d: xfail h8300.
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Since SHF_GNU_RETAIN is allowed on all sections, strip SHF_GNU_RETAIN
when checking incorrect section attributes.
PR gas/27412
* config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN
when checking incorrect section attributes.
* testsuite/gas/elf/elf.exp: Run section28 and section29.
* testsuite/gas/elf/section28.d: New file.
* testsuite/gas/elf/section28.s: Likewise.
* testsuite/gas/elf/section29.d: Likewise.
* testsuite/gas/elf/section29.s: Likewise.
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CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX
logic. Therefore it
- has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to
SSE2AVX translation and SSE checking,
- should not record MMX use in the respective ELF note.
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This undoes a change to md_assemble() that 32930e4edbc0 ("x86: Support
GNU_PROPERTY_X86_ISA_1_V[234] marker") did without any explanation. This
broke a CVTPI2PS property test that a subsequent test will add, and the
updates to existing tests also demonstrate what was wrong: For example,
AVX insns update the full YMM, even if a Vex128 variant is in use.
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VZERO{ALL,UPPER} modify YMM registers despite having no operands.
While {,V}{LD,ST}MXCSR don't modify XMM registers, MXCSR and XMMn
collectively form underlying machine state.
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There's no need to run the exact same test twice. Move the tests which
don't differ between 32- and 64-bit to the "Common tests" section.
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PR 27426
* dwarf2dbg.c (allocate_filename_to_slot): Allocate the dirs array
in another place.
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* read.c (demand_copy_C_string): Really check for embedded zeros.
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opcodes/
* s390-mkopc.c (main): Accept arch14 as cpu string.
* s390-opc.txt: Add new arch14 instructions.
include/
* opcode/s390.h (enum s390_opcode_cpu_val): Add
S390_OPCODE_ARCH14.
gas/
* config/tc-s390.c (s390_parse_cpu): New entry for arch14.
* doc/c-s390.texi: Document arch14 march option.
* testsuite/gas/s390/s390.exp: Run the arch14 related tests.
* testsuite/gas/s390/zarch-arch14.d: New test.
* testsuite/gas/s390/zarch-arch14.s: New test.
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follow links to separate debug info files.
* configure.ac (follow-debug-links): Add option to enable or
disable the following of debug links by default. Set the
default for the option to be 'follow'.
* dwarf.c (do_follow_links): Initialise with DEFAULT_FOR_FOLLOW_LINKS.
(dwarf_select_sections_by_names): Add no-follow-links option.
(dwarf_select_sections_by_letter): Add 'N' option.
* objdump.c (usage): Add conditional text describing the
follow links option.
(slurp_symtab): Ensure that there is a NULL entry at the end
of the symbol table.
(slurp_dynamic_symtab): Likewise.
(dump_bfd): When extending the symbol table, ensure that there
is still a NULL entry at the end.
* readelf.c (usage): Add conditional text describing the
follow links option.
* doc/binutils.texi: Update documentation for objcopy and
readelf.
* doc/debug.options.texi: Update documentation of the
follow-links option.
* config.in: Regenerate.
* configure: Regenerate.
* testsuite/binutils-all/compress.exp: Add the -WN option to
objdump command lines that are not expecting to follow links.
* testsuite/binutils-all/readelf.exp: Add the
--debug-dump=no-follow-links option to tests that are not
expecting to follow debug links.
gas * testsuite/gas/mach-o/sections-1.d: Stop automatic debug link
following.
* testsuite/gas/xgate/insns-dwarf2.d: Likewise.
ld * testsuite/ld-elf/sec64k.exp: Stop readelf from automatically
following debug links.
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Some hppa gas targets treat anything starting in the first column as a
label, so directives can't start there. Also, binutils_assemble and
run_dump_test cleverly edit test source to suit the hppa .comm
directive which has a different syntax to most targets. The editing
means we can't match source file names in dumps. Finally, hppa gas
complains if instructions are emitted without a ".text" or similar
directive.
* testsuite/gas/all/pr27381.err: Don't match source file name.
* testsuite/gas/all/pr27381.s: Don't start directive in first column.
* testsuite/gas/all/pr27384.err: Don't match source file name.
Adjust line number.
* testsuite/gas/all/pr27384.s: Add ".text" directive.
* testsuite/gas/elf/pr27355.err: Don't match source file name.
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gas/
* NEWS: Mention arm-symbianelf removal.
ld/
* NEWS: Mention arm-symbianelf removal.
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* listing.c (buffer_line): Remove debugging code accidentally
included with the fix for PR 27384.
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PR 27381
* read.c (s_incbin): Check that the file to be included is a
regular, non-directory file.
* testsuite/gas/all/pr27381.s: New test source file.
* testsuite/gas/all/pr27381.d: New test control file.
* testsuite/gas/all/pr27381.err: Expected error output for the new test.
* testsuite/gas/all/gas.exp: Run the new test.
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* configure.ac: Delete arm*-*-symbianelf* entry.
* configure: Regenerate.
bfd/
* config.bfd (arm*-*-symbianelf*): Move from obsolete to removed.
* configure.ac: Delete symbian entries.
* elf-bfd.h (enum elf_target_os): Delete is_symbian.
* elf32-arm.c: Remove symbian support. Formatting.
* targets.c: Delete symbian entries.
* configure: Regenerate.
binutils/
* testsuite/lib/binutils-common.exp (supports_gnu_osabi): Remove
symbianelf.
gas/
* Makefile.am (TARG_ENV_HFILES): Remove config/te-symbian.h.
* config/tc-arm.c (elf32_arm_target_format): Remove TE_SYMBIAN
support.
* config/te-symbian.h: Delete.
* configure.tgt: Remove arm-*-symbianelf*.
* testsuite/gas/arm/arch4t-eabi.d: Don't mention symbianelf in
target selection.
* testsuite/gas/arm/arch4t.d: Likewise.
* testsuite/gas/arm/got_prel.d: Likewise.
* testsuite/gas/arm/mapdir.d: Likewise.
* testsuite/gas/arm/mapmisc.d: Likewise.
* testsuite/gas/arm/mapsecs.d: Likewise.
* testsuite/gas/arm/mapshort-eabi.d: Likewise.
* testsuite/gas/arm/thumb-eabi.d: Likewise.
* testsuite/gas/arm/thumb.d: Likewise.
* testsuite/gas/arm/thumbrel.d: Likewise.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* Makefile.am (ALL_EMULATION_SOURCES): Remove earmsymbian.c.
Don't include symbian dep file.
* configure.tgt: Remove arm*-*-symbianelf* entry.
* emulparams/armsymbian.sh: Delete.
* ld.texi: Don't mention symbian.
* scripttempl/armbpabi.sc: Delete.
* testsuite/ld-arm/symbian-seg1.d: Delete.
* testsuite/ld-arm/symbian-seg1.s: Delete.
* testsuite/ld-arm/arm-elf.exp: Don't run symbian-seg1.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
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PR 27384
* listing.c (listing_psize): Check the result of the width
expression before assigning it to paper_width.
* testsuite/gas/all/pr27384.s: New test source file.
* testsuite/gas/all/pr27384.d: New test control file.
* testsuite/gas/all/pr27384.err: Expected errors from new test.
* testsuite/gas/all/gas.exp: Run the new test.
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trigger a segmentation fault.
PR 27355
* testsuite/gas/elf/pr27355.s: New test source file.
* testsuite/gas/elf/pr27355.d: New test control file.
* testsuite/gas/elf/pr27355.err: Expected errors from new test.
* testsuite/gas/elf/elf.exp: Run the new test.
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The tic54x exports some fairly generic variable names that can
conflict with programs that use them, so put proper tic54x_
prefixes on all of them.
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