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40 hoursgas: aarch64: suppport CFI directive .cfi_mte_tagged_frameIndu Bhagat1-0/+8
Process a new aarch64-specific CFI directive: .cfi_mte_tagged_frame (LLVM uses this CFI directive already). The CFI directive, when present for a function, indicates that the stack frame for the function may modify the MTE tags of the stack space it uses. The assembler emits char 'G' in the CIE augmentation string to indicate the same. ChangeLog: * gas/config/tc-aarch64.c (s_aarch64_mte_tagged_frame): New definition. * gas/config/tc-aarch64.h (tc_fde_entry_extras): Add memtag_frame_p. (tc_cie_entry_extras): Likewise. (tc_fde_entry_init_extra): Likewise. (tc_cie_fde_equivalent_extra): Likewise. (tc_cie_entry_init_extra): Likewise. * gas/doc/c-aarch64.texi: Add documentation for .cfi_mte_tagged_frame directive. * gas/testsuite/gas/aarch64/mte_tagged_stack.d: New test. * gas/testsuite/gas/aarch64/mte_tagged_stack.s: New test.
41 hoursaarch64: Add support for --march=armv9.6-aAlice Carlotti1-0/+1
41 hoursaarch64: Disable sysreg guards by defaultAlice Carlotti1-0/+6
Add a new flag -menable-sysreg-checking to restore previous behaviour. This existing behaviour is quite inconsistent, so the gating will probably be updated in the future. (In particular, many system registers are currently gated with the architecture version they were released with instead of the lower architecture version that they actually require). This patch retains the +d128 requirement for msrr/mrrs. Co-Authored-By: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
3 daysaarch64: Support for FEAT_SVE_AES2Ezra Sitorus1-0/+6
FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption Standard and 128-bit destination element polynomial multiply long instructions, when the PE is not in Streaming SVE mode.
3 daysaarch64: Support for FEAT_LSUIEzra Sitorus1-0/+2
FEAT_LSUI introduces unprivileged variants of load and store instructions so that clearing PSTATE.PAN is never required in privileged software.
4 daysRISC-V: Clarify the imply rule of cNelson Chu1-3/+5
This also fix the imply result for .option rvc. Imply zcf when c and f and rv32 Imply zcd when c and d Imply zca when c Changed INSN_CLASS_C to INSN_CLASS_ZCA Changed INSN_CLASS_F_AND_C to INSN_CLASS_ZCF Changed INSN_CLASS_D_AND_C to INSN_CLASS_ZCD Changed INSN_CLASS_ZIHINTNTL_AND_C to INSN_CLASS_ZIHINTNTL_AND_ZCA
4 daysRISC-V: Deprecate ".option arch, -ext" for users due to its controversial useNelson Chu1-16/+12
Before we figure out the whole remove situations for ".option arch, -ext", and have any RISC-V public spec defines it, we should just deprecate it.
5 daysaarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2Alice Carlotti1-0/+4
10 daysgas: introduce .errif and .warnifJan Beulich1-0/+16
Rather than having people resort to indirect means to issue a certain kind of diagnostic conditionally upon an expression which can (or should) only be evaluated when all sections were sized and all symbols had their final values established, provide directives to directly achieve this.
10 daysgas: add a means to programmatically determine the assembler versionJan Beulich1-0/+29
It has been more than once that I would have wanted to have a way to know the gas version in assembly sources, perhaps for use with .if. Add such a pre-defined symbol, introducing the common pattern GAS(<symbol>) for any such symbols. The use of parentheses is to keep the risk of collisions with users' symbols as low as possible. (Possible future arch-specific symbols may want to use GAS(<arch>:<symbol>).) Similarly permit determining whether the assembler is a released version. The exact value probably isn't of much use, it's more the defined-ness that one might care about. Yet the symbol needs to have some value anyway. While by default pre-defined symbols won't be emitted to the symbol table, introduce -emit-local-absolute to allow requesting this. Re- purpose flag_strip_local_absolute to become tristate, with a negative value indicating to also emit pre-defined symbols.
2025-06-25aarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
2025-06-24gas/doc: -v / -version / --version / --verboseJan Beulich1-2/+4
Split -v from -version/--version. They aren't the same; -v long form is --verbose, which so far wasn't mentioned at all.
2025-06-19aarch64: Support for FEAT_LSFEEzra Sitorus1-0/+2
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
2025-06-19aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
2025-06-19aarch64: Support for FEAT_CMPBREzra Sitorus1-0/+2
FEAT_CMPBR - Compare and branch instructions. This patch adds these instructions: - CB<CC> (register) - CB<CC> (immediate) - CBH<CC> - CBB<CC> where CC is one of the following: - EQ - NE - GT - GE - LT - LE - HI - HS - LO - LS
2025-06-19aarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+2
FEAT_OCCMO support was introduced, but the feature flags were missing. This patch adds these flags, as well as splitting up the tests to test occmo vs occmo+memtag operands.
2025-06-19aarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+2
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE and BFMUL.
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+2
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-05-23RISC-V: Add support for RISC-V Profiles 20/22.Jiawei2-5/+12
This patch introduces support for RISC-V Profiles RV20 and RV22 [1], enabling developers to utilize these profiles through the -march option. [1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0 bfd/ChangeLog: * elfxx-riscv.c (struct riscv_profiles): New struct. (riscv_parse_extensions): New argument. (riscv_find_profiles): New checking function. (riscv_parse_subset): Add Profiles handler. gas/ChangeLog: * NEWS: Add RISC-V Profiles. * doc/as.texi: Update -march input type. * doc/c-riscv.texi: Ditto. * testsuite/gas/riscv/option-arch-fail.l: Modify hint info. * testsuite/gas/riscv/attribute-17.d: New test. * testsuite/gas/riscv/attribute-18.d: New test. * testsuite/gas/riscv/march-fail-rvi20u64v.d: New test. * testsuite/gas/riscv/march-fail-rvi20u64v.l: New test.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu1-0/+21
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-04-09s390: Add support for z17 as CPU nameJens Remus2-3/+5
So far IBM z17 was identified as arch15. Add the real name, as it has been announced. [1] [1]: IBM z17 announcement letter, AD25-0015, https://www.ibm.com/docs/en/announcements/z17-makes-more-possible gas/ * config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU name for arch15. * doc/c-s390.texi: Likewise. * doc/as.texi: Likewise. opcodes/ * s390-mkopc.c (main): Add z17 as alternate CPU name for arch15. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-03-29x86: Add {noimm8s} pseudo prefixH.J. Lu1-0/+3
Instruction templates with only sign-extended 8-bit immediate operand also have a second template with full-operand-size immediate operand under a different opcode. Add {noimm8s} pseudo prefix to exclude templates with only sign-extended 8-bit immediate operand. gas/ PR gas/32811 * config/tc-i386.c (pseudo_prefixes): Add no_imm8s. (operand_size_match): Return false for templates with only sign- extended 8-bit immediate operand if {noimm8s} is used. (parse_insn): Handle Prefix_NoImm8s. * doc/c-i386.texi: Document {noimm8s}. * testsuite/gas/i386/pseudos.s: Add tests for {noimm8s}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/32811 * opcodes/i386-opc.h (Prefix_NoImm8s): New. * i386-opc.tbl: Add {noimm8s} pseudo prefix. * i386-mnem.h: Regenerated. * i386-tbl.h: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma1-0/+5
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-14gas: permit wider-than-byte operands for .cfi_escapeJan Beulich1-0/+12
Some DW_CFA_* and DW_OP_* take wider than byte, but non-LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-03-14gas: permit LEB128 operands for .cfi_escapeJan Beulich1-1/+12
Many DW_CFA_* and DW_OP_* take LEB128 operands. Having to hand-encode such when needing to resort to .cfi_escape isn't very helpful.
2025-02-14x86/APX: make .insn extended-EVEX capableJan Beulich1-2/+9
So far tricks had to be played to use .insn to encode extended-EVEX insns; the X4 bit couldn't be controlled at all. Extend the syntax just enough to cover all features, taking care to reject invalid feature combinations (albeit aiming at being as lax there as possible, to offer users as much flexibility as we can - we don't, after all, know what future will bring). In a pre-existing testcase replace all but one .byte; the one that needs to remain wants to have EVEX.U clear in a way that's neither controllable via AVX10/256 embedded rounding (would otherwise also set EVEX.ND), nor via the index register (EVEX.X4), as there's no memory operand. For one of the converted instances ModR/M.mod needs correcting: An 8-bit displacement requires that to be 1, not 2. Also adjust source comments to better represent what the bad insns mimic.
2025-02-14RISC-V: Add missing doc for OP_VKito Cheng1-0/+3
2025-02-14RISC-V: Add OP_VE for .insnKito Cheng1-0/+3
OP_VE is the opcode space for crypto vector instructions. Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#crypto-vector-cryptographic-instructions
2025-02-11RISC-V: Add .bfloat16 directiveKito Cheng1-0/+10
RISC-V already support bfloat16 instruciton like Zfbfmin, Zvfbfmin and Zvfbfwma, so I think it's reasonable to add .bfloat16 directive to support bfloat16 data type. And the code logic mostly support by common code already.
2025-02-07x86: Support x86 Zhaoxin PadLock XMODX instructionsMayShao-oc1-1/+3
The CPUID EDX bit[28] indicates its enablement, and it includes REP XMODEXP and REP MONTMUL2. XMODX stands for modular exponentiation, it indicates the support of modular exponentiation feature, both REP XMODEXP and REP MONTMUL2 use it. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock XMODX instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockXMODX instructions. (output_insn): Handle PadLockXMODX instructions. * doc/c-i386.texi: Document PadLockXMODX. * testsuite/gas/i386/i386.exp: Add PadLockXMODX test. * testsuite/gas/i386/padlockxmodx.d: Ditto. * testsuite/gas/i386/padlockxmodx.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockXMODX. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockXMODX): New. * i386-opc.tbl: Add Zhaoxin PadLock XMODX instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-31aarch64: Support +sme+nosve permissivelyAndrew Carlotti1-2/+2
There is inconsistency regarding whether or not +sme implies +sve2 and whether +nosve2 implies +nosme. In particular, GCC 14 assumes the dependency exists, and canonicalises target strings accordingly, whereas LLVM treats the features as independent. This patch removes the positive implication while retaining the negative implication. This is the more permissive choice in each case, and allows us to support target strings written with either interpretation in mind. This reduces our ability to detect invalid instructions, but we already can't rely on this detection because gas doesn't know whether functions might be executed in streaming mode and/or non-streaming mode. The aarch64_feature_enable_set change is functionally redundant within this patch. It is included because the longer term intention is to instead remove the workaround in aarch64_parse_features, once the internal feature checks have been modified to support having both AARCH64_FEATURE_SME set and AARCH64_FEATURE_SVE unset. Similarly, the dependency from +sme to +fp16 is currently redundant, but this redundancy relies upon an incorrect dependency from +fcma to +fp16. This can be fixed in the future, but it might require modifying internal feature checks for a few FCMA instructions, so it's left unchanged for now.
2025-01-31aarch64: Fix fp8 feature dependenciesAndrew Carlotti1-8/+8
We agreed with LLVM that we shouldn't enforce the architectural dependencies between fp8 muliplication features, so remove them. Additionally, fix a typo in the gating for FEAT_SME_F8F16 instructions, which were mistakenly gated by +sme-f8f32 instead. Until now this mistake had been masked by the dependency between the features.
2025-01-31aarch64: Fix overly lax +frintts dependencyAndrew Carlotti1-1/+1
We agreed with LLVM that +frintts should only enable +fp, not +simd. This also matches the dependency used in GCC.
2025-01-31x86: support RMPREAD insnJan Beulich1-2/+4
Like for RMPUPDATE documentation is about to change as far as operands are concerned. They're merely the other way around here. While adjustind gas documentation, also add the missing RMPQUERY counterparts there.
2025-01-31RISC-V: widen LEB128 supportJan Beulich1-4/+5
Do away with at least one of the limitations - all other targets permit multiple values to be specified with a single directive. Re-arrange the logic further to also overcome an internal error in riscv_insert_uleb128_fixes(), as e.g. observed by the all/sleb128-2 testcase. This way there's also no need to parse expressions twice, thus also not raising the same diagnostics (if any) twice. Note how this addresses a pre-existing XFAIL (where the comment wasn't really applicable either for RISC-V). Also update documentation, also to mention that differences between symbols may be used with .uleb128 (albeit I'm uncertain whether there are limitations).
2025-01-27Fix some broken links in docs and commentsYury Khrustalev2-6/+7
Reviewed-By Richard Earnshaw <richard.earnshaw@arm.com>
2025-01-22x86: Add missing @tab to separate columns in c-i386.texitimhu20111-2/+2
I have missed @tab for .gmiccs and .padlockphe2, so fix this doc error. gas/ChangeLog: * doc/c-i386.texi: Add the missing @tab for .gmiccs and .padlockphe2
2025-01-21Support broken gcc test for gas string merge supportAlan Modra1-1/+1
On casual reading of older gcc configure scripts it might be supposed that the test for gas string merge support tries with %progbits after a fail on ARM with @progbits. It doesn't succeed due to a bug. So to support building of older gcc's for ARM without users having to edit gcc sources, add a hack to gas. The hack can disappear in a few years when building older gcc's likely requires other work too. I've changed the docs to reflect what we actually allow for .section syntax prior to this patch. (No way should this hack be documented as allowed!) PR 32491 * config/obj-elf.c (obj_elf_section): Allow missing entsize for ARM gcc configure bug. * doc/as.texi: Correct syntax of ELF .section directive. * testsuite/gas/elf/string.s, * testsuite/gas/elf/string.d: Test it.
2025-01-20gas: elf: Relax rules for SHF_STRING sectionsRichard Earnshaw1-10/+18
Commit af3394d97a8c5187085c0eec5fb03e8da88db5fb allowed sections declared with "S" (SHF_STRING) to specify the entity size, but then would warn if the entity size was omitted, as with the old syntax. Unfortunately, since specifying the entity size is incompatible with binutils 2.43 or earlier, this makes it impossible to specify a strings section in source code without generating an assembly warning (the new syntax isn't supported in older assemblers and the old syntax generates warnings). Nevertheless, the old code was wrong in that it did not set the entity size at all, in contravention of the ELF specification (though to date there are no known cases where this mattered outside of mergeable sections). Fix this by permitting the original syntax without a warning again, but by defaulting the entity size to 1. This is compatible with the most common case of strings being byte-based. Added some tests for the various flavours of declaration that we support.
2025-01-17x86: Add CpuGMISM2 and CpuGMICCSMayShao-oc1-3/+4
There are separate CPUID feature bits for SM2 and CCS instructions. CCS is the acronym of Chinese Cipher System, it includes SM3 and SM4 instructions. This patch adds CpuGMISM2 and CpuGMICCS to replace CpuGMI on corresponding instructions. gas/ChangeLog: * config/tc-i386.c: Add gmism2 and gmiccs to replace gmi. * doc/c-i386.texi: Ditto. opcodes/ChangeLog: * i386-gen.c: Add GMISM2 and GMICCS to replace GMI. * i386-opc.h (enum i386_cpu): Add CpuGMISM2 and CpuGMICCS to replace CpuGMI. * i386-opc.tbl: Replace GMI with GMISM2 on sm2 instruction. Replace GMI with GMICCS on sm3 and sm4 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-16x86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc1-1/+3
The CPUID EDX bit[26] indicates its enablement, and it includes REP XSHA384 and REP XSHA512. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock PHE2 instructions. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLockPHE2 instructions. (output_insn): Handle PadLockPHE2 instructions. * doc/c-i386.texi: Document PadLockPHE2. * testsuite/gas/i386/i386.exp: Add PadLockPHE2 test. * testsuite/gas/i386/padlock_phe2.d: Ditto. * testsuite/gas/i386/padlock_phe2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockPHE2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockPHE2): New. * i386-opc.tbl: Add Zhaoxin PadLock PHE2 instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-14Support Intel AMX-AVX512Haochen Jiang1-1/+3
This patch will support AMX-AVX512. In disassmbler, we pull out all GPR mode out of the vex length switch to make it more general. gas/ChangeLog: * NEWS: Mention the full support on DMR AMX ISAs. * config/tc-i386.c: Add amx_avx512. * doc/c-i386.texi: Document .amx_avx512. * testsuite/gas/i386/x86-64.exp: Run AMX-AVX512 tests. * testsuite/gas/i386/x86-64-amx-avx512-intel.d: New test. * testsuite/gas/i386/x86-64-amx-avx512.d: Ditto. * testsuite/gas/i386/x86-64-amx-avx512.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h: Add EVEX_LEN_0F384A_X86_64_W_0, EVEX_LEN_0F386D_X86_64_W_0, EVEX_LEN_0F3A07_X86_64_W_0, EVEX_LEN_0F3A77_X86_64_W_0. * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A_W_0_L_2, PREFIX_EVEX_0F386D_W_0_L_2, PREFIX_EVEX_0F3A07_W_0_L_2, PREFIX_EVEX_0F3A77_W_0_L_2. * i386-dis-evex-w.h: Add EVEX_W_0F384A_X86_64, EVEX_W_0F386D_X86_64, EVEX_W_0F3A07_X86_64, EVEX_W_0F3A77_X86_64. * i386-dis-evex-x86-64.h: Add X86_64_EVEX_0F384A, X86_64_EVEX_0F386D, X86_64_EVEX_0F3A07, X86_64_EVEX_0F3A77. * i386-dis-evex.h: Ditto. * i386-dis.c (EVEX_LEN_0F384A_X86_64_W_0): New. (EVEX_LEN_0F386D_X86_64_W_0): Ditto. (EVEX_LEN_0F3A07_X86_64_W_0): Ditto. (EVEX_LEN_0F3A77_X86_64_W_0): Ditto. (MOD_EVEX_0F384A_X86_64_W_0): Ditto. (MOD_EVEX_0F386D_X86_64_W_0): Ditto. (MOD_EVEX_0F3A07_X86_64_W_0): Ditto. (MOD_EVEX_0F3A77_X86_64_W_0): Ditto. (PREFIX_EVEX_0F384A_W_0_L_2): Ditto. (PREFIX_EVEX_0F386D_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A07_W_0_L_2): Ditto. (PREFIX_EVEX_0F3A77_W_0_L_2): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (EVEX_W_0F386D_X86_64): Ditto. (EVEX_W_0F3A07_X86_64): Ditto. (EVEX_W_0F3A77_X86_64): Ditto. (X86_64_EVEX_0F384A): Ditto. (X86_64_EVEX_0F386D): Ditto. (X86_64_EVEX_0F3A07): Ditto. (X86_64_EVEX_0F3A77): Ditto. (OP_VEX): Pull out all GPR mode out of the vector length switch. * i386-gen.c (isa_dependencies): Add AMX-AVX512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_AVX512): New. (i386_cpu_flags): Add cpuamx_avx512. * i386-opc.tbl: Add AMX-AVX512 instructions. * i386-tbl.h: Regenerated.
2025-01-14Support Intel AMX-MOVRSHu, Lin11-1/+2
This patch will support AMX-MOVRS feature. Unlike all the other AMX insns in vector space where we pass vex_len_table before vex_w_table, we first pass vex_w_table for tileloaddrs[,t1] to align with the order in EVEX space. The reason why we first pass vex_w_table in EVEX space is due to AMX-AVX512, where tcvtrowd2ps and tilemovrow with r32 shares the same opcode with tileloaddrs[,t1]. All of them have evex.w = 0 but with different evex.length. Re-doing that shortly is not ideal. APX_F extension is also implemented in this patch. The encoding will be: - EVEX.128.NP/66.MAP5.W0 F8/F9 !(11):rrr:100 for T2RPNTLVW[Z0,Z1]RS[,T1] with NF=0. - EVEX.128.F2/66.0F38.W0 4A !(11):rrr:100 FOR TILELOADDRS[,T1] with NF=0. For APX_F extension, we could not use APX_F(AMX_TRANSPOSE&AMX_MOVRS) since the transformation could not be done. Instead, we will use AMX_TRANSPOSE & APX_F(AMX_MOVRS). Thus, we should set AMX_TRANSPOSE for "any" for cpu_flags in assembler. Since it will only affect the cpu_flags_match, handle that there. gas/ChangeLog: * config/tc-i386.c (cpu_arch): Add amx_movrs. (cpu_flags_match): Set any bitfield for multiple cpuid enabled insns. * doc/c-i386.texi: Document .amx_movrs. * testsuite/gas/i386/x86-64.exp: Run AMX-MOVRS tests. * testsuite/gas/i386/x86-64-amx-movrs-intel.d: New test. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-len.h (EVEX_LEN_0F384A_X86_64_W_0): New. * i386-dis-evex-w.h (EVEX_W_0F384A_X86_64): Ditto. * i386-dis-evex-x86-64.h (X86_64_EVEX_0F384A): Ditto. * i386-dis-evex.h: New entry for AMX-MOVRS. * i386-dis.c: (PREFIX_VEX_0F384A_X86_64_L_0_W_0): New. (PREFIX_VEX_MAP5_F8_X86_64_L_0_W_0): Ditto. (PREFIX_VEX_MAP5_F9_X86_64_L_0_W_0): Ditto. (X86_64_VEX_0F384A): Ditto. (X86_64_VEX_MAP5_F8): Ditto. (X86_64_VEX_MAP5_F9): Ditto. (X86_64_EVEX_0F384A): Ditto. (VEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_LEN_MAP5_F8_X86_64): Ditto. (VEX_LEN_MAP5_F9_X86_64): Ditto. (EVEX_LEN_0F384A_X86_64_W_0): Ditto. (VEX_W_0F384A_X86_64): Ditto. (VEX_W_MAP5_F8_X86_64): Ditto. (VEX_W_MAP5_F9_X86_64): Ditto. (EVEX_W_0F384A_X86_64): Ditto. (prefix_table): New entry for AMX-MOVRS. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map5_f8_opcode): New. (map5_f9_opcode): Ditto. (get_valid_dis386): Handle VEX_MAP5 opcode for AMX-MOVRS. * i386-gen.c (isa_dependencies): Add AMX_MOVRS. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_MOVRS): New. (i386_cpu_flags): Add cpuamx_movrs. * i386-opc.tbl: Add AMX-MOVRS instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-14Support Intel MOVRSHu, Lin11-0/+2
This patch focus on supporting MOVRS ISA. We could take this full ISA as four part: PREFETCHRST2, MOVRS, MOVRS APX_F extension and MOVRS AVX10.2 extension. The APX_F extension for MOVRS will be: - EVEX.LLZ.NP.MAP4.WIG 8A !(11):rrr:bbb for r8/m8 with NF=0 and ND=0 - EVEX.LLZ.NP/66.MAP4.SCALABLE 8B !(11):rrr:bbb for rv/mv with NF=0 and ND=0 We did not merge the table together for APX_F since there is an explicit x64 for movrs insn. The current APX_F() did not support the combination between CPUIDs. Also, the space is different for legacy and apx_f forms. gas/ChangeLog: * NEWS: Support Intel MOVRS. * config/tc-i386.c: Add MOVRS. * doc/c-i386.texi: Document .movrs. * testsuite/gas/i386/i386.exp: Run MOVRS tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Add MOVRS tests. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/lfence-load.d: Add prefetchrst2. * testsuite/gas/i386/lfence-load.s: Ditto. * testsuite/gas/i386/nops-8.d: Ditto. * testsuite/gas/i386/prefetch-intel.d: Ditto. * testsuite/gas/i386/prefetch.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.d: Ditto. * testsuite/gas/i386/x86-64-lfence-load.s: Ditto. * testsuite/gas/i386/x86-64-prefetch-intel.d: Ditto. * testsuite/gas/i386/x86-64-prefetch.d: Ditto. * testsuite/gas/i386/movrs-intel.d: New test. * testsuite/gas/i386/movrs-inval.l: Ditto. * testsuite/gas/i386/movrs-inval.s: Ditto. * testsuite/gas/i386/movrs.d: Ditto. * testsuite/gas/i386/movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-256.s: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.d: Ditto. * testsuite/gas/i386/x86-64-movrs-avx10_2-512.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel.d: Ditto. * testsuite/gas/i386/x86-64-movrs.d: Ditto. * testsuite/gas/i386/x86-64-movrs.s: Ditto. * testsuite/gas/i386/x86-64-movrs-intel-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.d: Ditto. * testsuite/gas/i386/x86-64-movrs-suffix.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_6F_X86_64. * i386-dis-evex-x86.h: Add X86_64_EVEX_MAP5_6F. * i386-dis-evex.h (evex_table): New entry for movrs. * i386-dis.c (MOD_0F18_REG_4): New. (PREFIX_EVEX_MAP5_6F_X86_64): Ditto. (X86_64_0F388A): Ditto. (X86_64_0F388B): Ditto. (X86_64_EVEX_MAP5_6F): Ditto. (three_byte_table): New entry for MOVRS. (reg_table): Ditto. (mod_table): Ditto. (x86_64_table): Ditto. Also include i386-dis-evex-x86.h. * i386-gen.c (cpu_flags): Add MOVRS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumovrs. * i386-opc.tbl: Add MOVRS instrctions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Lili Cui <lili.cui@intel.com>
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for FEAT_SME_F16F16 feature (Non-widening half-precision FP16 to FP16 arithmetic for SME2), which is enabled using command line flags +sme-f16f16 to -march (which enables both FEAT_SME2 and FEAT_SME_F16F16). There are couple of instructions (fadd and fsub variants) which should be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16. Those instructions are already supported in the current assembler, this patch adds tests for those instructions as well.
2025-01-10x86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc1-2/+3
This patch adds support for Zhaoxin PadLock RNG2 instruction, the CPUID EDX bit[23] indicates its enablement, it includes REP XRNG2 instruction. gas/ChangeLog: * NEWS: Support Zhaoxin PadLock RNG2 instruction. * config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to PadLock RNG2 instruction. (output_insn): Handle PadLock RNG2 instruction. * doc/c-i386.texi: Document PadLock RNG2. * testsuite/gas/i386/i386.exp: Add PadLock RNG2 test. * testsuite/gas/i386/padlock_rng2.d: Ditto. * testsuite/gas/i386/padlock_rng2.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add PadLockRNG2. * i386-gen.c: Ditto * i386-opc.h (CpuPadLockRNG2): New. * i386-opc.tbl: Add Zhaoxin PadLock RNG2 instruction. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2025-01-08Support Intel AMX-FP8Liwei Xu1-1/+2
In this patch, we will support AMX-FP8 feature. Since in the foreseeable future, only AMX-MOVRS will also use VEX_MAP5, we currently will not add a table of 256 entries and handle just like MAP7. gas/ChangeLog: * config/tc-i386.c: Add amx_fp8. * doc/c-i386.texi: Document .amx_fp8. * testsuite/gas/i386/x86-64.exp: Run AMX-FP8 tests. * testsuite/gas/i386/x86-64-amx-fp8-bad.d: New test. * testsuite/gas/i386/x86-64-amx-fp8-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-fp8-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.d: Ditto. * testsuite/gas/i386/x86-64-amx-fp8.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0): New. (X86_64_VEX_MAP5_FD): Ditto. (VEX_LEN_MAP5_FD_X86_64): Ditto. (VEX_W_MAP5_FD_X86_64_L_0):Ditto. (prefix_table): Add PREFIX_VEX_MAP5_FD_X86_64_L_0_W_0. (x86_64_table): Add X86_64_VEX_MAP5_FD. (vex_len_table): Add VEX_LEN_MAP5_FD_X86_64. (vex_w_table): Add VEX_W_MAP5_FD_X86_64_L_0. * i386-gen.c: Add CPU_AMX_FP8_FLAGS and CPU_ANY_AMX_FP8_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: Add cpuamx_fp8. * i386-opc.tbl: Add AMX_FP8 instructions. * i386-tbl.h: Regenerated. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2025-01-02gas: Revert PR 32391 related commits to fix 3 regressionsH.J. Lu1-59/+1
9f2e3c21f65 Fix the handling or arguments and macro pseudo-variables inside nested assembler macros. introduced 3 regressions of PR gas/32484, PR gas/32486 and PR gas/32487. Revert all PR 32391 related commits and add tests for PR gas/32484, PR gas/32486, PR gas/32487. PR gas/32484 PR gas/32486 PR gas/32487 * testsuite/gas/macros/macros.exp: Run nesting1, nesting2 and nesting3. * testsuite/gas/macros/nesting1.d: New file. * testsuite/gas/macros/nesting1.s: Likewise. * testsuite/gas/macros/nesting2.d: Likewise. * testsuite/gas/macros/nesting2.s: Likewise. * testsuite/gas/macros/nesting3.d: Likewise. * testsuite/gas/macros/nesting3.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
generated by cgit v1.1 at 2025-07-14 01:53:26 +0000