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AgeCommit message (Expand)AuthorFilesLines
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-31/+0
2021-01-07ELF: Don't generate unused section symbolsH.J. Lu1-0/+3
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich1-0/+2
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf1-1/+13
2021-01-06RISC-V: Implement support for big endian targets.Marcus Comstedt2-7/+27
2021-01-04elf: Allow mixed ordered/unordered inputs for non-relocatable linkH.J. Lu1-1/+3
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra3-5/+5
2021-01-01Update year range in copyright notice of binutils filesAlan Modra237-237/+237
2021-01-01gas: Change to "swym 0" as canonical nop insn for MMIXHans-Peter Nilsson1-1/+1
2020-12-16constify elfNN_bedAlan Modra1-16/+11
2020-12-16PR27071, gas bugs uncovered by fuzzingAlan Modra2-1/+22
2020-12-11Add support for the .bss pseudo-op to the Z80 assembler.Nick Clifton1-0/+10
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu1-0/+33
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu1-4/+10
2020-12-08gas: Generate a new section for SHF_GNU_RETAINH.J. Lu2-18/+20
2020-12-01RISC-V: Support to add implicit extensions.Nelson Chu1-1/+3
2020-12-01RISC-V: Improve the version parsing for arch string.Nelson Chu1-13/+10
2020-11-23aarch64: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+9
2020-11-18Support SHF_GNU_RETAIN ELF section flagJozef Lawrynowicz1-17/+63
2020-11-16aarch64: Add +pauth flag for Pointer Authentication featurePrzemyslaw Wirkus1-0/+2
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus1-0/+2
2020-11-16arm: Add support for Cortex-A78CPrzemyslaw Wirkus1-0/+3
2020-11-13gas, arm: PR26858 Fix availability of single precision vmul/vmla in arm modeAndre Vieira1-2/+2
2020-11-12MSP430: gas: Ignore -md option required for GCC backward compatibilityJozef Lawrynowicz1-0/+8
2020-11-09gas: improve reproducibility for stabs debugging data formatDenys Zagorui1-1/+2
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-1/+2
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+16
2020-11-09RISC-V: Update ABI to the elf_flags after parsing elf attributes.Nelson Chu1-47/+55
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-0/+2
2020-11-03gas: fix symbol value calculation for versioned symbol aliasesChristian Eggers1-1/+2
2020-10-30x86: Support GNU_PROPERTY_X86_ISA_1_BASELINE markerH.J. Lu1-42/+50
2020-10-29aarch64: Fix DSB instruction 'missing immediate expression' errorsPrzemyslaw Wirkus1-1/+5
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+31
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+47
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+1
2020-10-26C-SKY: Fix the literal dump of big vector constant.Cooper Qu1-1/+2
2020-10-26CSKY: Add version flag in eflag and fix bug in disassembling register.Cooper Qu1-1/+1
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu1-0/+12
2020-10-22arm: Fix the wrong error message string for mve vldr/vstr (PR26763).Srinath Parvathaneni1-1/+9
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert1-1/+1
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+2
2020-10-16Enhancement for avx-vnni patchCui,Lili1-8/+8
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-1/+11
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+3
2020-10-14x86: Support Intel UINTRLili Cui1-0/+3
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-24/+19
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-30/+45
2020-10-09x86: Support GNU_PROPERTY_X86_ISA_1_V[234] markerH.J. Lu1-61/+65
2020-10-06aarch64: Fix bogus type punning in parse_barrier() [PR26699]Alex Coplan1-7/+1
2020-10-06A small set of code improvements for the Z80 assembler.Sergey Belyashav1-7/+21
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