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2019-01-08[AArch64][gas] Add -mcpu support for Arm AresKyrylo Tkachov1-0/+5
2019-01-07[arm][gas] Add -mcpu support for Arm AresKyrylo Tkachov1-0/+3
2019-01-05RX: gas - Add RXv3 instruction support.Yoshinori Sato3-50/+338
2019-01-01Update year range in copyright notice of binutils filesAlan Modra234-234/+234
2018-12-19x86: Properly handle PLT expression in directiveH.J. Lu1-3/+14
2018-12-14elf: Add PT_GNU_PROPERTY segment typeH.J. Lu1-1/+0
2018-12-13Move aarch64 CIE code to aarch64 backendSam Tebbs1-0/+37
2018-12-10RISC-V: Don't segfault for two regs in auipc or lui.Jim Wilson1-1/+8
2018-12-09x86: Put back BFD_RELOC_X86_64_GOTPCRELH.J. Lu1-0/+1
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson1-3/+12
2018-12-06PowerPC @l, @h and @ha warnings, plus VLE e_liAlan Modra1-33/+55
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-2/+2
2018-12-05[aarch64] Add support for pointer authentication B keySam Tebbs1-0/+9
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-140/+23
2018-12-01PR23938, should not free memory alloced in obstack by free()Alan Modra3-3/+3
2018-11-30GAS/MIPS: Add `-mfix-r5900' option for the R5900 short loop erratumFredrik Noring1-1/+24
2018-11-27RISC-V: Add .insn CA support.Jim Wilson1-0/+31
2018-11-27Tighten the constraints for warning about NOPs for the MSP 430 ISA, so NOPs a...Jozef Lawrynowicz1-61/+235
2018-11-21S12Z: Add alias instructions BHS and BLO.John Darrington1-0/+2
2018-11-13[ARM] Improve indentation of ARM architecture declarationsThomas Preud'homme1-51/+51
2018-11-12[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das1-3/+17
2018-11-12[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das1-0/+6
2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das1-0/+2
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das1-0/+2
2018-11-09S/390: Fix optional operand handling after memory addressesAndreas Krebbel1-24/+23
2018-11-09PowerPC, don't use bfd reloc howto in md_assembleAlan Modra1-11/+249
2018-11-07rx: Add target rx-*-linux.Yoshinori Sato1-0/+4
2018-11-06[arm] Check for neon and condition in vcvt.f16.f32Matthew Malcomson1-0/+2
2018-11-06PowerPC instruction mask checksAlan Modra1-14/+23
2018-11-06PowerPC instruction operand flag validationAlan Modra1-0/+9
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-2/+2
2018-11-05x86: Disable GOT relaxation with data prefixH.J. Lu1-6/+7
2018-10-29Move struc-symbol.h to symbols.cAlan Modra20-116/+75
2018-10-28PR23837, Segmentation fault in resolve_symbol_valueAlan Modra1-2/+1
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel1-0/+15
2018-10-23S12Z: Handle 16 bit fixups which are constant.John Darrington1-0/+3
2018-10-22Apply alpha BFD_RELOC_8 fixupsAlan Modra1-0/+6
2018-10-20PR23800, .eqv doesn't always defer expression evaluationAlan Modra1-1/+16
2018-10-19This set of changes clarifies the conditions for the R5900 short loop fix and...Fredrik Noring1-5/+17
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-6/+6
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das1-0/+52
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das1-0/+17
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+2
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+1
2018-10-05[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32Sudakshina Das1-0/+13
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das1-0/+12
2018-10-05[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32Sudakshina Das1-0/+2
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+6