riscv-gnu-toolchain/binutils.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-07-04	RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issue	Sun Sunny	1	-1/+4
2024-07-04	RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hi	Lifang Xia	1	-7/+17
2024-06-12	RISC-V: Support S[sm]csrind extension csrs.	Jiawei	1	-0/+22
2024-06-05	RISC-V: Add support for XCVbi extension in CV32E40P	Mary Bennett	1	-1/+11
2024-05-20	RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to...	Sung-hun Kim	1	-1/+1
2024-04-09	RISC-V: Support Zcmp push/pop instructions.	Jiawei	1	-0/+181
2024-03-28	RISC-V: Removed privileged spec 1.9.1 support in assembler.	Nelson Chu	1	-2/+3
2024-03-13	RISC-V: Add -march=help for gas	Hau Hsu	1	-0/+6
2024-02-29	RISC-V: Add assembly support for TLSDESC.	Tatsuyuki Ishi	1	-5/+13
2024-02-21	RISC-V: Don't generate branch/jump relocation if symbol is local when no-relax.	Nelson Chu	1	-0/+8
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma	1	-0/+79
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2023-12-22	RISC-V: drop .bss override	Jan Beulich	1	-10/+0
2023-12-12	Fix whitespace snafu in tc-riscv.c	Nick Clifton	1	-5/+5
2023-12-12	RISC-V: Emit R_RISCV_RELAX for the la/lga pseudo instruction	Rui Ueyama	1	-0/+15
2023-12-12	RISC-V: Resolve PCREL_HI20/LO12_I/S fixups with local symbols while `-mno-relax'	Lifang Xia	1	-0/+108
2023-12-11	RISC-V/gas: Clarify the definition of `relaxable' in md_apply_fix	Nelson Chu	1	-1/+1
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	1	-0/+68
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-16/+5
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich	1	-3/+3
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	1	-0/+4
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	1	-0/+14
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	1	-0/+28
2023-11-03	RISC-V: reduce redundancy in load/store macro insn handling	Jan Beulich	1	-85/+6
2023-11-03	RISC-V: make FLQ/FSQ macro-insns work	Jan Beulich	1	-0/+10
2023-10-27	RISC-V: Clarify the behaviors of SET/ADD/SUB relocations.	Nelson Chu	1	-0/+1
2023-10-16	RISC-V: Add "lp64e" ABI support	Tsukasa OI	1	-1/+3
2023-10-02	Fix memory leak in RiscV assembler.	Nick Clifton	1	-0/+1
2023-09-20	elf-attrs.c memory allocation fail	Alan Modra	1	-4/+11
2023-09-18	Fix: Use of uninitialized memory	Jacob Navia	1	-1/+1
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu	1	-85/+97
2023-09-05	RISC-V: fold duplicate code in vector_macro()	Jan Beulich	1	-40/+5
2023-09-05	RISC-V: Add 'Smcntrpmf' extension and its CSRs	Tsukasa OI	1	-0/+9
2023-09-01	RISC-V: Fixed the wrong expansion for pseudo vmsge[u].vx instructions.	Nelson Chu	1	-4/+4
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich	1	-1/+1
2023-08-02	Revert "2.41 Release sources"	Sam James	1	-2/+57
2023-08-02	2.41 Release sourcesbinutils-2_41-release	Nick Clifton	1	-57/+2
2023-07-25	RISC-V: Enable RVC on ".option arch, +zca" etc.	Tsukasa OI	1	-1/+2
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei	1	-0/+53
2023-07-18	RISC-V: Support Zca/f/d extensions.	Jiawei	1	-1/+2
2023-07-01	RISC-V: Add support for the Zvbb ISA extension	Christoph Müllner	1	-0/+13
2023-06-30	RISC-V: Add support for the Zfa extension	Christoph Müllner	1	-0/+52
2023-06-19	riscv: Use run-time endianess for floating point literals	Andreas Schwab	1	-1/+1
2023-06-01	RISC-V: PR30449, Add lga assembler macro support.	Jim Wilson	1	-2/+6
2023-05-19	RISC-V: Support subtraction of .uleb128.	Kuan-Lin Chen	1	-2/+54
2023-05-04	RISC-V: tighten post-relocation-operator separator expectation	Jan Beulich	1	-1/+3
2023-04-25	RISC-V: adjust logic to avoid register name symbols	Jan Beulich	1	-27/+94
2023-04-25	RISC-V: don't recognize bogus relocations	Jan Beulich	1	-2/+1
2023-04-25	RISC-V: avoid redundant and misleading/wrong error messages	Jan Beulich	1	-0/+9
2023-04-25	RISC-V: drop "percent_op" parameter from my_getOpcodeExpression()	Jan Beulich	1	-4/+4