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| author | Mary Bennett <mary.bennett@embecosm.com> | 2023-10-02 03:02:05 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-07 12:06:27 +0800 |
| commit | ccb388ca39f49b611acadce03916837c9c1c1ed1 (patch) | |
| tree | c55e0441952e6b2c821000718ded7b3b3501cf60 /gas/config/tc-riscv.c | |
| parent | cf0d07fd07117934750e4bb94cfc0349e251afae (diff) | |
| download | binutils-ccb388ca39f49b611acadce03916837c9c1c1ed1.zip binutils-ccb388ca39f49b611acadce03916837c9c1c1ed1.tar.gz binutils-ccb388ca39f49b611acadce03916837c9c1c1ed1.tar.bz2 | |
RISC-V: Add support for XCVmac extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html
Contributors:
Mary Bennett <mary.bennett@embecosm.com>
Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Pietra Ferreira <pietra.ferreira@embecosm.com>
Charlie Keaney
Jessica Mills
Craig Blackmore <craig.blackmore@embecosm.com>
Simon Cook <simon.cook@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Helene Chelin <helene.chelin@embecosm.com>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
instruction class.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Added the necessary
operands for the extension.
(riscv_ip): Likewise.
* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
for CORE-V.
* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
* testsuite/gas/riscv/cv-mac-insns.d: New test.
* testsuite/gas/riscv/cv-mac-insns.s: New test.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Disassemble information with
the EXTRACT macro implemented.
* riscv-opc.c: Defined the MASK and added
XCVmac instructions.
include/ChangeLog:
* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
for XCVmac.
* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
for uimm.
(enum riscv_insn_class): Added the XCVmac instruction class.
Diffstat (limited to 'gas/config/tc-riscv.c')
| -rw-r--r-- | gas/config/tc-riscv.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 30e14bb..29676bc 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1481,6 +1481,16 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) } } break; + case 'c': /* Vendor-specific (CORE-V) operands. */ + switch (*++oparg) + { + case '3': + used_bits |= ENCODE_CV_IS3_UIMM5 (-1U); + break; + default: + goto unknown_validate_operand; + } + break; default: goto unknown_validate_operand; } @@ -3581,6 +3591,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, } break; + case 'c': /* Vendor-specific (CORE-V) operands. */ + switch (*++oparg) + { + case '3': + my_getExpression (imm_expr, asarg); + check_absolute_expr (ip, imm_expr, FALSE); + asarg = expr_parse_end; + if (imm_expr->X_add_number < 0 + || imm_expr->X_add_number > 31) + break; + ip->insn_opcode + |= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number); + continue; + default: + goto unknown_riscv_ip_operand; + } + break; + default: goto unknown_riscv_ip_operand; } |