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2024-10-30x86: add a helper to copy insn operand infoJan Beulich1-133/+44
We're doing such in fairly many places, and yet more are likely to appear; centralize the logic, much like we already have swap_2_operands(). While there also correct mis-indentation in adjacent code in process_operands().
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich1-4/+23
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich1-1/+3
We should not (silently) emit a REX prefix ahead of a REX2-encoded insn; such encodings are illegal. Best we can do is fold the REX bits into the REX2 prefix, and then zap the REX one from i.prefix[].
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich1-4/+4
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-0/+1
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-15x86: Refine instruction check in x86_check_tls_relocationCui, Lili1-10/+11
gas/ChangeLog: * config/tc-i386.c (x86_check_tls_relocation): Refine instruction check.
2024-10-11x86: bring 64-bit-only cmdline option handling in syncJan Beulich1-2/+8
--64 and --x32 are already suppressed in --help output when BFD64 is not defined. Also avoid recognizing these options in such configurations.
2024-10-04x86: prune OBJ_MAYBE_... usesJan Beulich1-162/+108
With the removal of emulations, OBJ_MAYBE_... can no longer be defined. Tidy code wherever they're used, which also includes the dropping of most IS_ELF and uses and checks of OUTPUT_FLAVOR. Where touching such constructs anyway, also drop TE_PEP checks when used together with TE_PE ones (the former implies the latter).
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich1-0/+96
They are equivalent to simple moves or xors, which are up to 3 bytes shorter to encode (and maybe/likely also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich1-0/+74
They, too, are equivalent to simple moves, which are up to 3 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich1-0/+36
They are equivalent to simple moves, which are up to 2 bytes shorter to encode (and maybe also cheaper to execute).
2024-09-27x86: correct {,V}PEXTR{D,Q} optimizationJan Beulich1-0/+1
A possible relocation associated with a memory operand also needs moving.
2024-09-26x86 TLS relocation checksAlan Modra1-7/+8
Some configurations (eg. i386-bsd, i386-msdos) broke with the addition of the TLS relocation checking. The "x86_elf_abi undeclared" error has been fixed, but "gotrel defined but not used" remains. Fix that. Also invert the preprocessor test around lex_got to make it positive logic and remove the LEX_AT condition which is no longer necessary. (The only x86 config files defining LEX_AT also define TE_PE.)
2024-09-24x86: Enable TLS relocation check only for ELFH.J. Lu1-11/+11
Since TLS relocation check is ELF specific, enable it only for ELF. PR gas/32022 * config/tc-i386.c (x86_tls_error_type): Define only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (x86_check_tls_relocation): Likewise. (x86_report_tls_error): Likewise. (i386_assemble): Check TLS relocations only if OBJ_MAYBE_ELF or OBJ_ELF is defined. (md_show_usage): Output -mtls-check= only if OBJ_MAYBE_ELF or OBJ_ELF is defined. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-23Fix compile time error introduced by ↵Nick Clifton1-2/+8
d774bf9b3623239a1cfa729afcf048a15da657d3 for non-ELF x86 targets
2024-09-23x86: Turn PLT32 to PC32 only for PC-relative relocationsH.J. Lu1-1/+10
commit 292676c15a615b5a95bede9ee91004d3f7ee7dfd Author: H.J. Lu <hjl.tools@gmail.com> Date: Thu Feb 13 13:44:17 2020 -0800 x86: Resolve PLT32 reloc aganst local symbol to section resolved PLT32 relocation against local symbol to section and commit 2585b7a5ce5830e60a089aa2316a329558902f0c Author: H.J. Lu <hjl.tools@gmail.com> Date: Sun Jul 19 06:51:19 2020 -0700 x86: Change PLT32 reloc against section to PC32 turned PLT32 relocation against section into PC32 relocation. But these transformations are valid only for PC-relative relocations. Add fx_pcrel check for PC-relative relocations when performing these transformations to keep PLT32 relocation in `movq $foo@PLT, %rax`. gas/ PR gas/32196 * config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel for PLT32 relocations. (i386_validate_fix): Turn PLT32 relocation into PC32 relocation only if fixp->fx_pcrel is set. * testsuite/gas/i386/reloc32.d: Updated. * testsuite/gas/i386/reloc64.d: Likewise. * testsuite/gas/i386/reloc32.s: Add PR gas/32196 test. * testsuite/gas/i386/reloc64.s: Likewise. ld/ PR gas/32196 * testsuite/ld-x86-64/plt3.s: New file. * testsuite/ld-x86-64/x86-64.exp: Run plt3. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-21x86: Add tls check in gasCui, Lili1-22/+416
Assembler shouldn't accept invalid TLS instructions, TLS relocations can only be used with specific instructions as specified in TLS psABI and linker issues an error when TLS relocations are used with wrong instructions or format. Since it is inconvenient for gcc to rely on linker to report errors, adding TLS check in the assembler stage so that gcc can know TLS errors earlier. gas/ChangeLog: PR gas/32022 * config.in: Regenerate. * config/tc-i386.c *(enum x86_tls_error_type): New. *(struct _i386_insn): Added has_gotrel to indicate whether TLS relocations need to be checked. (x86_check_tls_relocation): Added a new function to check TLS relocation. (x86_report_tls_error): Created a new function to report TLS error. (i386_assemble): Handle x86_check_tls_relocation. (lex_got): Set i.has_gotrel. (OPTION_MTLS_CHECK): Added a new option to contrl TLS check. (struct option): Ditto. (md_parse_option): Ditto. (md_show_usage): Ditto. * configure.ac: Added a new option to check TLS relocation by default. * configure: Regenerated. * doc/c-i386.texi: Document -mtls-check=. * testsuite/gas/i386/i386.exp: Added new tests. * testsuite/gas/i386/ilp32/ilp32.exp: Ditto. * testsuite/gas/i386/ilp32/reloc64.d: Disable TLS check for it. * testsuite/gas/i386/ilp32/x32-tls.d: Ditto. * testsuite/gas/i386/inval-tls.l: Added more test cases. * testsuite/gas/i386/inval-tls.s: Ditto. * testsuite/gas/i386/reloc32.d: Disable TLS check for it. * testsuite/gas/i386/reloc64.d: Ditto. * testsuite/gas/i386/x86-64-inval-tls.l: Added more test cases. * testsuite/gas/i386/x86-64-inval-tls.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added new tests. * testsuite/gas/i386/ilp32/x32-inval-tls.l: New test. * testsuite/gas/i386/ilp32/x32-inval-tls.s: Ditto. * testsuite/gas/i386/ilp32/x86-64-tls.d: Ditto. * testsuite/gas/i386/tls.d: Ditto. * testsuite/gas/i386/tls.s: Ditto. * testsuite/gas/i386/x86-64-tls.d: Ditto. * testsuite/gas/i386/x86-64-tls.s: Ditto. ld/ChangeLog: PR gas/32022 * testsuite/ld-i386/tlsgdesc1.d: Disable TLS check for it. * testsuite/ld-i386/tlsgdesc2.d: Ditto. * testsuite/ld-i386/tlsie2.d: Ditto. * testsuite/ld-i386/tlsie3.d: Ditto. * testsuite/ld-i386/tlsie4.d: Ditto. * testsuite/ld-i386/tlsie5.d: Ditto. * testsuite/ld-i386/tlsgdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc3.d: Ditto. * testsuite/ld-x86-64/tlsdesc4.d: Ditto. * testsuite/ld-x86-64/tlsie2.d: Ditto. * testsuite/ld-x86-64/tlsie3.d: Ditto. * testsuite/ld-x86-64/tlsie5.d: Ditto. * testsuite/ld-x86-64/tlsdesc5.d: Ditto.
2024-09-20x86-64: Never make R_X86_64_GOT64 section relativeH.J. Lu1-0/+1
R_X86_64_GOT64 relocation should never be made section relative. Change tc_i386_fix_adjustable to return 0 for BFD_RELOC_X86_64_GOT64. gas/ PR gas/32189 * config/tc-i386.c (tc_i386_fix_adjustable): Return 0 for BFD_RELOC_X86_64_GOT64. * testsuite/gas/i386/reloc64.d: Updated. * testsuite/gas/i386/reloc64.s: Add more tests for R_X86_64_GOT64 and R_X86_64_GOTOFF64. ld/ PR gas/32189 * testsuite/ld-x86-64/x86-64.exp: Run PR gas/32189 test. * testsuite/ld-x86-64/pr32189.s: New file. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-09-11x86: error handling in set_cpu_arch()Jan Beulich1-30/+34
Error messages there would better not be followed by further "junk at end of line" diagnostics. Arrange for this to be the case uniformly. While there also replace a somewhat unhelpful open-coding of restore_line_pointer().
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich1-1/+7
There's no need to have 30 redundant templates when we can easily take care of the operand swapping like we do for various other insns.
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich1-0/+35
Along the lines of 2513312930b2 ("x86/APX: apply NDD-to-legacy transformation to further CMOVcc forms") these can similarly be converted to the shorter legacy-encoded CMOVcc.
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang1-56/+64
In the patch, in order to support ymm rounding for AVX10.2, we derive evex attribute for all cases instead of only for rc_none to encode U bit. Also changed some bad_opcode return due to the share of U bit with APX_F. gas/ChangeLog: * config/tc-i386.c (cpu_flags_match): Handle AVX10_2. (build_evex_prefix): Handle U bit. Derive evex attribute for all cases. (check_VecOperands): Handle AVX10.2 and ymm roundings. * doc/c-i386.texi: Document .avx10.2. * testsuite/gas/i386/i386.exp: Run AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: New test. * testsuite/gas/i386/avx10_2-rounding-inval.l: Ditto. * testsuite/gas/i386/avx10_2-rounding-inval.s: Ditto. * testsuite/gas/i386/avx10_2-rounding.d: Ditto. * testsuite/gas/i386/avx10_2-rounding.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-rounding.s: Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add U bit. (get_valid_dis386): Handle U bit. * i386-gen.c (isa_dependencies): Add AVX10.2. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX10_2): New. (i386_cpu_flags): Add cpuavx10_2. * i386-opc.tbl: Add rounding to old entries which do not permit rounding previously. Also eliminate the redundant RegXMM for vcvtps2uqq. * i386-tbl.h: Regenerated.
2024-08-30x86: replace conditional operators used to calculate booleansJan Beulich1-10/+11
The boolean expressions themselves are fine to use there.
2024-08-30x86: limit RegRex64 useJan Beulich1-9/+7
The special property really only applies to the "extended" byte regs having legacy word/dword counterparts. While touching involved code also drop redundant byte checks from a conditional in establish_rex(): The other remaining RegRex64 uses only exist on registers which can't be used as register operands anyway. Hence RegRex64 as an attribute of a (valid) register operand implies that it's a byte reg.
2024-08-28x86: Report invalid TLS operatorH.J. Lu1-2/+2
Report invalid TLS operator, instead of relocation. PR gas/28595 * config/tc-i386.c (gotrel): Replace int with unsigned int. (i386_assemble): Report invalid TLS operator. * testsuite/gas/i386/inval-tls.l: updated. * testsuite/gas/i386/x86-64-inval-tls.l: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Report invalid TLS relocation nameH.J. Lu1-91/+98
Get TLS relocation name from its lex_got entry when reporting invalid instructions with TLS relocations. PR gas/28595 * config/tc-i386.c (gotrel): Moved from ... (lex_got): There. (i386_assemble): Get invalid TLS relocation name from its lex_got entry when reporting TLS relocation error. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-27x86: Allow R_386_TLS_LE_32 with KMOVDH.J. Lu1-2/+2
Since there is no TLS IE transition, allow R_386_TLS_LE_32 with KMOVD. gas/ PR gas/28595 * config/tc-i386.c (i386_assemble): Remove BFD_RELOC_386_TLS_LE_32 from TLS code check. * testsuite/gas/i386/inval-tls.s: Remove foo@tpoff(%eax). * testsuite/gas/i386/inval-tls.l: Updated. ld/ PR gas/28595 * testsuite/ld-i386/i386.exp: Run tlsle1. * testsuite/ld-i386/tlsle1.d: New file. * testsuite/ld-i386/tlsle1.s: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-08-23x86: simplify SAE checkingJan Beulich1-12/+10
To determine whether SAE (with or without StaticRounding) is permitted there's no need to iterate over all operands. Even less so starting at the front (thus needlessly inspecting immediate operands as well). Leverage the pattern across all relevant templates and check only the last two operands, and also only for non-512 ones (besides the non-LIG case that was already checked for).
2024-08-14x86: correct .insn with opcode extension and VEX/XOP/EVEX encodingJan Beulich1-1/+2
When VexVVVV handling was re-worked, .insn broke: When an opcode extension is in use, VexVVVV_DST needs using now, as ModR/M.reg is already occupied, matching what c8866e3ec5e2 ("x86: Drop using extension_opcode to encode vvvv register") did. While adding (bad) POP2 forms, also slightly adjust existing ones: No need to use XMM registers, and no need to specify %r8 when really %rax is meant twice (EVEX.vvvv not really being the culprit there, or else EVEX.V' would also have needed mentioning).
2024-07-31x86: move ginsn stuffJan Beulich1-1102/+3
This had been badly inserted between md_assemble() and its helpers anyway. Follow what was done for Arm64 and move the code to its own file, #include-d as appropriate.
2024-07-26x86: accept whitespace around prefix separatorJan Beulich1-19/+30
... and prediction suffix comma. Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks around these separators wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. Furthermore note how, due to the scrubber being overly aggressive in removing whitespace, some similar construct with a prefix were already accepted. Note how certain other checks in parse_insn() can be simplified as a result. While there for the prediction suffix also make checks case-insensitive and check for a proper trailing separator.
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich1-0/+107
..., as those leave EFLAGS untouched anyway. That's a shorter encoding, available as long as no eGPR is in use anywhere.
2024-07-19x86: accept whitespace inside curly bracesJan Beulich1-5/+18
Other than documented /**/ comments currently aren't really converted to a single space, at least not for x86 in its most common configurations. That'll be fixed subsequently, at which point blanks may appear where so far none were expected. Furthermore not permitting blanks immediately inside curly braces wasn't quite logical anyway - such constructs are composite ones, and hence components ought to have been permitted to be separated by whitespace from the very beginning. With this we also don't care anymore whether the scrubber would remove whitespace around curly braces, so move them from extra_symbol_chars[] to operand_special_chars[]. Note: The new testcase doesn't actually exercise much (if any) of the added code. It is being put in place to ensure that subsequently, when that code actually comes into play, behavior remains the same.
2024-07-19x86: undo '{' being a symbol-start characterJan Beulich1-14/+98
Having it that way has undue side effects, in permitting not only pseudo-prefixes to be parsed correctly, but also permitting odd symbol names which ought to be possible only when quoted. Borrow what other architectures do: Put in place an "unrecognized line" hook to parse off any pseudo prefixes, while using the "start of line" hook to reject ones not actually followed by an insn. For that parsing re-use parse_insn() in yet a slightly different mode (dealing with only pseudo-prefixes). With that, pp may no longer be cleared from init_globals(), but instead needs clearing after a line was fully processed. Since md_assemble() has pretty many return paths, convert that into a local helper, with a trivial wrapper around it. Similarly pp may no longer be updated (by check_register()) when processing anything other than insn operands. To be able to (easily) recognize the case, clear current_templates.start when done with an insn (or with .insn).
2024-07-19x86: split pseudo-prefix state from i386_insnJan Beulich1-196/+197
Subsequently we will want to update that ahead of md_assemble(), with that function needing to take into account such earlier updating. Therefore it'll want resetting separately from i.
2024-07-19x86/APX: add CMPcc/CTESTcc cases to noreg64 testsJan Beulich1-11/+29
This was missed when support for the insns was added. Just like for DATA16, in rex64 neg (%rax) rex64 neg (%r16) rex64 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the prefix.
2024-07-12x86/APX: remove two inconsistenciesJan Beulich1-18/+23
As indicated in earlier discussion, permitting GOTTPOFF uniformly for all legacy non-SIMD insns while at the same time restricting to just certain ADD forms when EVEX-encoded is inconsistent. Make promoted insns "equal" to their legacy original ones. Doing that adjustment prevents another inconsistency, too: In data16 neg (%rax) data16 neg (%r16) data16 {nf} neg (%rax) it is not logical why the last one shouldn't be permitted. Bypassing that check requires other adjustments, though, to actually properly consume (and then squash) the data size prefix. While there also add the missing CMP and TEST cases to the test case being modified.
2024-07-12x86/APX: correct TEST/CTESTcc with 1st operand being a memory oneJan Beulich1-4/+8
While they properly inherited D and C, code processing the reversal of operands wasn't updated accordingly (and "reversed" operands also weren't tested anywhere).
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
Added the restriction in assemble for APX TLS IE that the destination can only be a register. gas/ * config/tc-i386.c (md_assemble): Added stricter restrictions for APX TLS IE.
2024-07-04gas: Enhance arch-specific SFrame configuration descriptionsJens Remus1-0/+5
Explicitly mention "SFrame" in the descriptions for the architecture- specific SFrame configuration macros, variables, and functions. Use the term "frame pointer" (FP) instead of "base pointer". This aligns with the terminology used in the SFrame specification. Additionally it helps not to confuse "base-pointer register" with the term "BASE_REG" used in the specification to denote either the SP or FP register. Specify what the SFRAME_CFA_*_REG register numbers are used for: - SP (stack pointer): CFA tracking - FP (frame pointer): CFA and FP tracking - RA (return address): RA tracking Align the descriptions for definitions in the source files to the declarations in the header files. gas/ * config/tc-aarch64.h: Enhance architecture-specific SFrame configuration descriptions. * config/tc-aarch64.c: Likewise. * config/tc-i386.h: Likewise. * config/tc-i386.c: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04x86: Remove unused SFrame CFI RA register variableJens Remus1-1/+0
gas/ * config/tc-i386.c (x86_sframe_cfa_ra_reg): Remove. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-07-04Support APX CFCMOVCui, Lili1-1/+1
The CMOVcc instruction proposed by EVEX has four different forms, corresponding to the four possible combinations of EVEX.ND and EVEX.NF values. In the encoder part, when the CFCMOV template supports EVEX_NF, it means that it requires EVEX.NF to be 1. In the decoder part, CFCMOV_Fixup is used to reverse source and destination operands in the 2-operand case. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov when the insn template supports EVEX_NF. * testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov. * testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto. * testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add cfcmov instructions. * i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov. (putop): Print 'cf' for cfcmov instructions. * i386-opc.h (EVEX_NF): New. * i386-opc.tbl: Add cfcmov instructions. * i386-mnem.h: Regerated. * i386-tbl.h: Regerated.
2024-07-03x86-64: Support APX NF TLS IE with 2 operandsLingling Kong1-2/+8
Support APX NF TLS IE with 2 operands.Verify it with ld and gold. gas/ * config/tc-i386.c (md_assemble): Allow APX NF TLS IE with 2 operands. * testsuite/gas/i386/x86-64-gottpoff.d: Updated. * testsuite/gas/i386/x86-64-gottpoff.s: Add APX NF TLS IE tests with 2 operands. gold/ * testsuite/x86_64_ie_to_le.s: Add APX NF TLS IE tests with 2 operands. * testsuite/x86_64_ie_to_le.sh: Updated. ld/ * testsuite/ld-x86-64/tlsbindesc.s: Add APX NF TLS IE tests with 2 operands. * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich1-1/+16
With both sources being registers, these insns are almost commutative; the only extra adjustment needed is inversion of the encoded condition.
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich1-2/+8
The same properties apply there.
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich1-0/+70
..., for differing only in the resulting EFLAGS, which are left untouched anyway. That's a shorter encoding, available as long as certain constraints on operands are met; see code comments. (SHL-by-1 forms may then be subject to further optimization that was introduced earlier.) Note that kind of as a side effect this also converts multiplication by 1 to shift by 0, which is a plain move or even no-op anyway. That could be further shrunk (as could be presence of shifts/rotates by 0 in the original code as well as a fair set of other {nf}-form insns), yet the expectation (for now) is that people won't write such code in the first place.
2024-06-28x86-64: restrict by-imm31 optimizationJan Beulich1-12/+15
Avoid changing the encoding when there's no size gain: If there's a REX or REX2 prefix anyway and the base opcode wouldn't be changed, dropping just REX.W / REX2.W has no (size) effect. (Same for the AND-by-imm7 case in the same big conditional.) While there also pull out the .qword check: For the 2-register-operands case whether that's done on the 1st or 2nd operand doesn't matter. Due to reduction in necessary parentheses this improves readability a tiny bit.
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich1-8/+236
..., as that leaves EFLAGS untouched anyway. That's a shorter encoding, available as long as certain constraints on operand size and registers are met; see code comments. Note that this requires deferring to derive encoding_evex from {nf} presence, as in optimize_encoding() we want to avoid touching the insns when {evex} was also used. Note further that this requires want_disp32() to now also consider the opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still report the original mnemonic (or else things can get confusing). While there, correct adjacent mis-indentation.
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich1-1/+21
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS.CF, for the NF variants the immediate can be got rid of in that case by switching to a 1-bit rotate in the opposite direction.
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich1-1/+83
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS, for the NF variants we can safely replace ones using 0x80 by the respectively other insn while negating the immediate, saving 3 immediate bytes (just 1 though for 16-bit operand size). Similarly we can replace ones using 1 / -1 by INC/DEC (eliminating the immediate).
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