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ChangeLog
2025-01-16 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* binutils/NEWS: Updated.
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The bug was filed against gprofng-gui (https://savannah.gnu.org/bugs/?66560).
gprofng/ChangeLog
2025-01-16 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* src/Hist_data.cc (DbeInstr::mapPCtoLine): Check for null pointer.
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Many FEAT_SVE2p1 instructions need to be enabled by either of two
different features (one for streaming mode, and one for non-streaming
mode). This patch adds correct gating conditions for these
instructions.
There were also a few sve2p1 instructions missing altogether, so add
those as well.
The testsuite is modified to check for all alternative enablement
conditions. In many cases this is done by adding an alternative
assembler commands to existing test files. For some SME/SME2 tests,
only some of the instructions are enabled by +sve2p1, so these are
copied into a separate test. For original SVE2p1 tests, the non-SME2p1
instructions have been moved to a separate test file.
There are also new tests for the newly added instructions. These
include a couple of fixme comments relating to bad error reporting,
which should be investigated later.
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The base class mapped_index_base is no longer needed. Previously it
was used by both the .gdb_index and .debug_names readers, but the
latter now uses the cooked index instead.
This patch removes mapped_index_base, merging it into
mapped_gdb_index. Supporting code that is specific to .gdb_index is
also moved into read-gdb-index.c. This shrinks dwarf2/read.c a bit,
which is nice.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32504
Approved-By: Andrew Burgess <aburgess@redhat.com>
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gdb_index_unpack is not used and can be removed. The include of
extract-store-integer.h is also no longer needed by this file.
Approved-By: Andrew Burgess <aburgess@redhat.com>
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I found a number of .c files that need to include
extract-store-integer.h but that were only including it indirectly.
This patch adds the missing includes. This change enables the next
patch.
Approved-By: Andrew Burgess <aburgess@redhat.com>
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Fedora has been carrying this test since back in the Project Archer
days. A change back then caused GDB to stop being able to backtrace when
only some of the object files had debug information. Even though the
changed code never seems to have made its way into the main GDB project,
I think it makes sense to bring the test along to ensure something like
this doesn't pass unnoticed.
Co-Authored-By: Jan Kratochvil <jan@jankratochvil.net>
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Andrew Burgess <aburgess@redhat.com>
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Sometimes, in the GDB testsuite, we want to test the ability of specific
unwinders to handle some piece of code. Usually this is done by trying
to outsmart GDB, or by coercing the compiler to remove information that
GDB would rely on. Both approaches have problems as GDB gets smarter
with time, and that compilers might differ in version and behavior, or
simply introduce new useful information. This was requested back in 2003
in PR backtrace/8434.
To improve our ability to thoroughly test GDB, this patch introduces a
new maintenance command that allows a user to disable some unwinders,
based on either the name of the unwinder or on its class. With this
change, it will now be possible for GDB to not find any frame unwinders
for a given frame, which would previously cause GDB to assert. GDB will
now check if any frame unwinder has been disabled, and if some has, it
will just error out instead of asserting.
Unwinders can be disabled or re-enabled in 3 different ways:
* Disabling/enabling all at once (using '-all').
* By specifying an unwinder class to be disabled (option '-class').
* By specifying the name of an unwinder (option '-name').
If you give no options to the command, GDB assumes the input is an
unwinder class. '-class' would make no difference if used, is just here
for completeness.
This command is meant to be used once the inferior is already at the
desired location for the test. An example session would be:
(gdb) start
Temporary breakpoint 1, main () at omp.c:17
17 func();
(gdb) maint frame-unwinder disable ARCH
(gdb) bt
\#0 main () at omp.c:17
(gdb) maint frame-unwinder enable ARCH
(gdb) cont
Continuing.
This commit is a more generic version of commit 3c3bb0580be0,
and so, based on the final paragraph of the commit message:
gdb: Add switch to disable DWARF stack unwinders
<...>
If in the future we find ourselves adding more switches to disable
different unwinders, then we should probably move to a more generic
solution, and remove this patch.
this patch also reverts 3c3bb0580be0
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=8434
Co-Authored-By: Andrew Burgess <aburgess@redhat.com>
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Andrew Burgess <aburgess@redhat.com>
temp adding completion
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Frame unwinders have historically been a structure populated with
callback pointers, so that architectures (or other specific unwinders)
could install their own way to handle the inferior. However, since
moving to C++, we could use polymorphism to get the same functionality
in a more readable way. Polymorphism also makes it simpler to add new
functionality to all frame unwinders, since all that's required is
adding it to the base class.
As part of the changes to add support to disabling frame unwinders,
this commit makes the first baby step in using polymorphism for the
frame unwinders, by making frame_unwind a virtual class, and adds a
couple of new classes. The main class added is frame_unwind_legacy,
which works the same as the previous structs, using function pointers
as callbacks. This class was added to allow the transition to happen
piecemeal. New unwinders should instead follow the lead of the other
classes implemented.
2 of the others, frame_unwind_python and frame_unwind_trampoline, were added
because it seemed simpler at the moment to do that instead of reworking
the dynamic allocation to work with the legacy class, and can be used as
an example to future implementations.
Finally, the cygwin unwinder was converted to a class since it was most
of the way there already.
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Approved-By: Andrew Burgess <aburgess@redhat.com>
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A future patch will add a way to disable certain unwinders based on
different characteristics. This patch aims to make it more convenient
to disable related unwinders in bulk, such as architecture specific
ones, by identifying all unwinders by which part of the code adds it.
The classes, and explanations, are as follows:
* GDB: An internal unwinder, added by GDB core, such as the unwinder
for dummy frames;
* EXTENSION: Unwinders added by extension languages;
* DEBUGINFO: Unwinders installed by the debug info reader;
* ARCH: Unwinders installed by the architecture specific code.
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Approved-By: Andrew Burgess <aburgess@redhat.com>
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Before this commit, all frame unwinders would be stored in the obstack
of a gdbarch and accessed by using the registry system. This made for
unwieldy code, and unnecessarily complex logic in the frame_unwinder
implementation, along with making frame_unwind structs be unable to have
non-trivial destructors.
Seeing as a future patch of this series wants to refactor the
frame_unwind struct to use inheritance, and we'd like to not restrict
the future derived classes on what destructors are allowed. In
preparation for that change, this commit changes the registry in gdbarch
to instead store an std::vector, which doesn't require using an obstack
and doesn't rely on a linked list.
There should be no user-visible changes.
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Approved-By: Andrew Burgess <aburgess@redhat.com>
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There are separate CPUID feature bits for SM2 and CCS instructions.
CCS is the acronym of Chinese Cipher System, it includes SM3 and SM4
instructions. This patch adds CpuGMISM2 and CpuGMICCS to replace CpuGMI on
corresponding instructions.
gas/ChangeLog:
* config/tc-i386.c: Add gmism2 and gmiccs to replace gmi.
* doc/c-i386.texi: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Add GMISM2 and GMICCS to replace GMI.
* i386-opc.h (enum i386_cpu): Add CpuGMISM2 and CpuGMICCS to
replace CpuGMI.
* i386-opc.tbl: Replace GMI with GMISM2 on sm2 instruction. Replace GMI
with GMICCS on sm3 and sm4 instructions.
* i386-tbl.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-init.h: Ditto.
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The type transition of TLSDESC is only done when -mrelax is enabled.
So when -mno-relax is enabled, keep GOT_TLS_GDESC to allocate the
GOT entry instead of just keeping GOT_TLS_IE.
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cpu_flags_match() is a hot path. Move the special casing that
b7267244a355 ("Support Intel AMX-MOVRS") added there to i386-gen, thus
affecting only build time performance.
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Deriving operand size may no longer assume 512-bit vector size when
embedded rounding is in use. In fact it was apparently wrong to do so
in the first place, as that's not correct for scalar insns. Drop the
rounding type check altogether; we fall back to EVEX.LIG when no
suitable operand was specified anyway, later in the function (and, btw,
similarly for VEX encodings).
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Even though the relocation isn't IRELATIVE, it still should be come last if
refering to ifunc symbol. In order to get the ifunc relocs properly sorted
the correct class needs to be returned. The code mimics what has been done
for x86, sparc, aarch64 and arm32.
bfd/
PR 18841
PR 32499
* elfnn-riscv.c (riscv_reloc_type_class): Handle ifunc relocation
ordering, even though it's not IRELATIVE, it still should be come
last if refering ifunc symbol.
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Free ofilename on error path. Don't bother testing "if (foo)" before
"free (foo)".
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Seen running ld-plugin/lto-4r-c on x86_64-w64-mingw32
* ldlang.c (cmdline_add_object_only_section): Allocate one more
for output symbol buffer.
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The ".quad with division (fwdref)" gas test fails with asan warning
negation of -9223372036854775808 cannot be represented in type 'long int'
Fix this and another similar case.
* symbols.c (resolve_symbol_value): Cast "left" to valueT
before negating.
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Load the object only section when opening the mixed object file, instead
of loading it after all other input files have been loaded. This fixed
.../ld/collect-ld: /tmp/ccZAoUIW.obj-only.o: in function `main':
.../ld/testsuite/ld-plugin/lto-10a.c:4: multiple definition of `main'; /usr/x86_64-w64-mingw32/sys-root/mingw/lib/../lib/libmingw32.a(lib64_libmingw32_a-crtexewin.o):(.text.startup+0x0): first defined here
.../ld/collect-ld: /usr/x86_64-w64-mingw32/sys-root/mingw/lib/../lib/libmingw32.a(lib64_libmingw32_a-crtexewin.o):(.text.startup+0xc5): undefined reference to `WinMain'
collect2: error: ld returned 1 exit status
...
FAIL: LTO 10
for x86_64-w64-mingw32 so that mixing LTO and non-LTO relocatable files
for "ld -r" works for both ELF and non-ELF platforms.
* ld.texi: Remove "On ELF platforms" from documentation of mixing
LTO and non-LTO relocatable files for "ld -r".
* ldlang.c (cmdline_load_object_only_section): New.
(cmdline_check_object_only_section): Call it.
* testsuite/ld-plugin/lto.exp: Enable mixed LTO and non-LTO
relocatable output tests for all.
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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score_elf_create_dynamic_relocation sets up three output dynamic
relocs from rel[0], rel[1] and rel[2]. When rel[0] is the last reloc
in a section this of course results in a buffer overflow. It's a
weird thing to do given that only one relocation is output.
* elf32-score.c (score_elf_create_dynamic_relocation): Do not
set up three dynamic relocations when only one is output.
* elf32-score7.c: Likewise.
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* elf64-mmix.c (mmix_elf_relocate_section): Correct size of
relocs shuffled by memmove.
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No path to "cleanup" label has internal_relocs malloc'd.
* emultempl/xtensaelf.em (replace_insn_sec_with_prop_sec): Don't
free internal_relocs in cleanup.
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This change is to make tail conform with software guarded jump of Zicfilp. The
reason to not choose t1 as the label register is that t1 is also as .got.plt
offset of _dl_runtime_resolve in PLT.
See more: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93
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https://github.com/riscv/riscv-cfi/releases/tag/v1.0
This patch only support the CFI instructions and CSR in assembler.
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https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0
The privileged spec v1.10 already removed the sfence.vm instruction, and the
encoding of sfence.vm instruction is overlapped with the sctrclr instruction
of ssctr/smctr. But since the privileged spec v1.10 already removed the
sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we
had to remove the sfence.vm.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr.
(riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0.
(riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr.
(riscv_multi_subset_supports_ext): Likewise.
gas/
* config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address):
Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR.
(riscv_is_priv_insn): Removed SFENCE_VM check.
* testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no
longer supported since privileged spec v1.10.
* testsuite/gas/riscv/attribute-14.s: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr.s: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr.
* testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction.
* testsuite/gas/riscv/smctr-ssctr.s: Likewise.
include/
* opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed
encoding macro for sfence.vm since encoding conflict. Added CSR
numbers for ssctr/smctr CSRs.
* opcode/riscv.h (enum riscv_insn_class): Added
INSN_CLASS_SMCTR_OR_SSCTR for sctrclr.
opcodes/
* riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm
since encoding conflict.
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map.xml contains a checksum for all Elf files.
gprofng-archive archives a file only with the same checksum.
In gprofng-display-text no additional check is required.
gprofng/ChangeLog
2025-01-15 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* src/parse.cc: Don't check Elf when file is in archive.
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Apparently reflex doesn't have yyalloc.
* ldlex.l (yy_create_string_buffer): Revert last change.
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of reporting bad for disassembler
According to SDM, vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd treat
Rounding as Ignored when trying to using them. Thus, disassembler
should accept bytecode with rounding instead of reporting bad.
For assembler, it needs some more time to decide how to deal
with that.
gas/ChangeLog:
* testsuite/gas/i386/evex.d: Add new testcase for vcvt[,u]dq2pd.
Change the output for vcvt[,u]si2sd.
* testsuite/gas/i386/evex.s: Ditto.
* testsuite/gas/i386/x86-64-evex.d: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-w.h: Add EXxEVexR64 for vcvt[,u]dq2pd.
* i386-dis.c (OP_Rounding): Mark EVEX_b as used to change the handle
for ignored rounding.
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* plugin.c (plugin_get_ir_dummy_bfd): Free bfd filename.
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* ldlex.l (<<EOF>>): yy_delete_buffer current.
(yy_create_string_buffer): Use yyalloc.
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There isn't much sense in stashing contents in sec->contents
after those contents have been written.
* ldelf.c (write_build_id): Don't assign sec->contents.
Free contents if malloc'd here.
(write_package_metadata): Likewise.
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* ldelf.c (ldelf_search_needed): Free filename before returning.
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* ldfile.c (ldfile_remap_input_free): Make static, call from..
(ldfile_free): ..here. New function.
(ldfile_library_path_free, ldfile_script_free),
( ldfile_arch_free): New functions.
(ldfile_find_command_file): Free script_dir. Move
script_search to file scope.
(ldfile_open_command_file_1): Delete FIXME comment.
* ldfile.h (ldfile_remap_input_free): Delete.
(ldfile_free): Declare.
* ldlang.c (lang_finish): Update.
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This frees output_section_statement data, which is currently only used
by elf targets but doing so for all targets is simpler and more
future proof than adding ths to ldelf_finish. (Doing it there
requires moving the function to ldelfgen.c.)
* ldemul.c (finish_default): Free os->data.
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Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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When running test-case gdb.dwarf2/implptr.exp on target board unix/-m32, we
get:
...
(gdb) PASS: gdb.dwarf2/implptr.exp: print ***l in implptr:bar
break implptr.c:34^M
No compiled code for line 34 in file "implptr.c".^M
Make breakpoint pending on future shared library load? (y or [n]) n^M
(gdb) FAIL: $exp: set baz breakpoint for implptr (got interactive prompt)
...
This is a regression since commit dcaa85e58c4 ("gdb: reject inserting
breakpoints between functions").
The .debug_line info does not contain an entry with a line number lower than
36, so gdb cannot map it to an address.
Fix this by setting a breakpoint at the function containing line 34 instead.
Tested on x86_64-linux.
PR testsuite/32477
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=32477
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The CPUID EDX bit[26] indicates its enablement, and it includes REP
XSHA384 and REP XSHA512.
gas/ChangeLog:
* NEWS: Support Zhaoxin PadLock PHE2 instructions.
* config/tc-i386.c (add_branch_prefix_frag_p): Don't add prefix to
PadLockPHE2 instructions.
(output_insn): Handle PadLockPHE2 instructions.
* doc/c-i386.texi: Document PadLockPHE2.
* testsuite/gas/i386/i386.exp: Add PadLockPHE2 test.
* testsuite/gas/i386/padlock_phe2.d: Ditto.
* testsuite/gas/i386/padlock_phe2.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c: Add PadLockPHE2.
* i386-gen.c: Ditto
* i386-opc.h (CpuPadLockPHE2): New.
* i386-opc.tbl: Add Zhaoxin PadLock PHE2 instructions.
* i386-tbl.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-init.h: Ditto.
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This fixes leaks in a ppc disassembler buffer. I'm not sure now why I
used a private buffer for section contents, but I'm not going to
change that just now.
* disassemble.h (disassemble_free_powerpc): Declare.
* disassemble.c (disassemble_free_target): Call it.
* ppc-dis.c (disassemble_free_powerpc): New function.
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* elf32-ppc.c (add_stub_sym): Alloc the sym name.
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* config/tc-ppc.c (ppc_machine): Free cpu_string.
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I've freed htab->relr in two places, first when we're done with it
in ppc64_elf_build_stubs, and also when freeing the hasn table to
catch cases where the linker exits early due to errors.
* elf64-ppc.c (ppc64_elf_link_hash_table_free): Free htab->relr.
(ppc64_elf_build_stubs): Also free it here.
(ppc_add_stub): Copy stub_name when creating..
(ppc64_elf_size_stubs): ..and always free stub_name.
(opd_entry_value): Free sym.
(ppc_build_one_stub): bfd_alloc stub sym name.
(build_global_entry_stubs_and_plt): Likewise.
(ppc64_elf_setup_section_lists): bfd_zalloc htab->sec_info.
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This adds the section to HANDLE_ALIGN args, so that the frag created
by the ppc backend can be properly allocated on the frag obstack.
I've added an extra param to frag_alloc too, for cases where we know
the frag requires at least some bytes in fr_literal. This simplifies
some existing code, for example in compress_debug and relax_segment.
In the case of the relax_segment code, I think we may have had a bug
there in using obstack_blank_fast, which doesn't check that the frag
has room.
* config/tc-ppc.c (ppc_handle_align): Add section param,
use frag obstack to allocate frag.
* config/tc-ppc.h (HANDLE_ALIGN, ppc_handle_align): Add extra
param.
* config/tc-aarch64.h (HANDLE_ALIGN): Add extra param.
* config/tc-alpha.h: Likewise.
* config/tc-arc.h: Likewise.
* config/tc-arm.h: Likewise.
* config/tc-avr.h: Likewise.
* config/tc-epiphany.h: Likewise.
* config/tc-frv.h: Likewise.
* config/tc-i386.h: Likewise.
* config/tc-ia64.h: Likewise.
* config/tc-kvx.h: Likewise.
* config/tc-loongarch.h: Likewise.
* config/tc-m32c.h: Likewise.
* config/tc-m32r.h: Likewise.
* config/tc-metag.h: Likewise.
* config/tc-mips.h: Likewise.
* config/tc-mn10300.h: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-riscv.h: Likewise.
* config/tc-rl78.h: Likewise.
* config/tc-rx.h: Likewise.
* config/tc-sh.h: Likewise.
* config/tc-sparc.h: Likewise.
* config/tc-spu.h: Likewise.
* config/tc-tilegx.h: Likewise.
* config/tc-tilepro.h: Likewise.
* config/tc-v850.h: Likewise.
* config/tc-visium.h: Likewise.
* config/tc-wasm32.h: Likewise.
* config/tc-xtensa.h: Likewise.
* frags.h (frag_alloc): Update prototype.
* frags.c (frag_alloc): Add extra size param, allocate extra.
(frag_new): Update.
* subsegs.c (subseg_set_rest): Update frag_alloc call.
* write.c: Formatting.
(cvt_frag_to_fill): Pass sec to HANDLE_ALIGN.
(compress_frag): Update frag_alloc call.
(compress_debug): Use new frag_alloc to simplify frag sizing.
(relax_segment): Likewise.
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This fixes leaks of outsymbols for various targets that use the
generic linker. The key fix here is to not generate output symbols
for targets that won't ever write symbols, and of course to free
outsymbols after they've been written in targets that do. Target
vector object_flags and section_flags are updated to better reflect
target capabilities, in particular not setting HAS_SYMS or SEC_RELOC
when the target does not support symbols or relocs.
* binary.c (binary_vec): Update section_flags.
* linker.c (generic_add_output_symbol): Don't add to
outsymbols if !HAS_SYMS.
* srec.c (srec_write_symbols): Free outsymbols on return.
(srec_vec): Update object_flags and section_flags.
(symbolsrec_vec): Likewise.
* tekhex.c (tekhex_write_object_contents): Free outsymbols on
return.
(tekhex_vec): Update object_flags and section_flags.
* verilog.c (verilog_vec): Likewise.
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