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| author | Nelson Chu <nelson@rivosinc.com> | 2025-01-17 12:20:30 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-01-17 12:34:56 +0800 |
| commit | 93056786a1a73b5f9f79cfd966d2616297deec41 (patch) | |
| tree | d32568a64cd08722c1de8a2682e35ae7bc4e7cf8 | |
| parent | 1c618df71307a9b1403c55ade463bf23e1d7e770 (diff) | |
| download | binutils-93056786a1a73b5f9f79cfd966d2616297deec41.zip binutils-93056786a1a73b5f9f79cfd966d2616297deec41.tar.gz binutils-93056786a1a73b5f9f79cfd966d2616297deec41.tar.bz2 | |
gas/NEWS: Updated risc-v assembler support in 2.44.
| -rw-r--r-- | gas/NEWS | 11 |
1 files changed, 8 insertions, 3 deletions
@@ -23,9 +23,14 @@ * On x86 emulation support (for secondary targets) was dropped. -* Add support for RISC-V Zcmp (cm.mva01s, cm.mvsa01), Smrnmi, S[sm]dbltrp, - CORE-V (xcvbitmanip, xcvsimd) extensions with version 1.0 and more SiFive - extensions (xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf). +* Add support for RISC-V standard extensions, + Zicfiss v1.0, Zicfilp v1.0, Zcmp v1.0 (cm.mva01s and cm.mvsa01 instructions), + Zcmt v1.0, Smrnmi v1.0, S[sm]dbltrp v1.0 and S[sm]ctr v1.0 (replaced the + dropped sfence.vm encoding since privileged spec v1.10). + +* Add support for RISC-V vendor extensions, + CORE-V, xcvbitmanip v1.0 and xcvsimd v1.0. + SiFive, xsfvqmaccdod v1.0, xsfvqmaccqoqv1.0 and xsfvfnrclipxfqf v1.0. Changes in 2.43: |