RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.

https://github.com/riscv/riscv-cfi/releases/tag/v1.0

This patch only support the CFI instructions and CSR in assembler.

21 files changed, 259 insertions, 0 deletions

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f354ba0..9354886 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1220,6 +1220,9 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcmop", "+zca", check_implicit_always},
   {"zcmt", "+zca,+zicsr",	check_implicit_always},
 
+  {"zicfilp", "+zicsr", check_implicit_always},
+  {"zicfiss", "+zimop,+zicsr", check_implicit_always},
+
   {"shcounterenw", "+h", check_implicit_always},
   {"shgatpa", "+h", check_implicit_always},
   {"shtvala", "+h", check_implicit_always},
@@ -1355,6 +1358,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zihpm",		ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zimop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicfiss",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicfilp",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"za64rs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"za128rs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2581,6 +2586,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zihintpause");
     case INSN_CLASS_ZIMOP:
       return riscv_subset_supports (rps, "zimop");
+    case INSN_CLASS_ZICFISS:
+      return riscv_subset_supports (rps, "zicfiss");
+    case INSN_CLASS_ZICFISS_AND_ZCMOP:
+      return riscv_subset_supports (rps, "zicfiss")
+	     && riscv_subset_supports (rps, "zcmop");
+    case INSN_CLASS_ZICFILP:
+      return riscv_subset_supports (rps, "zicfilp");
     case INSN_CLASS_M:
       return riscv_subset_supports (rps, "m");
     case INSN_CLASS_ZMMUL:
@@ -2830,6 +2842,19 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zicsr";
     case INSN_CLASS_ZIFENCEI:
       return "zifencei";
+    case INSN_CLASS_ZICFISS:
+      return "zicfiss";
+    case INSN_CLASS_ZICFISS_AND_ZCMOP:
+      if (!riscv_subset_supports (rps, "zicfiss"))
+	{
+	  if (!riscv_subset_supports (rps, "zcmop"))
+	    return _("zicfiss' and `zcmop");
+	  else
+	    return "zicfiss";
+	}
+      return "zcmop";
+    case INSN_CLASS_ZICFILP:
+      return "zicfilp";
     case INSN_CLASS_ZIHINTNTL:
       return "zihintntl";
     case INSN_CLASS_ZIHINTNTL_AND_C:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2fcde21..e219dd2 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -72,6 +72,7 @@ enum riscv_csr_class
   CSR_CLASS_F,		/* f-ext only */
   CSR_CLASS_ZKR,	/* zkr only */
   CSR_CLASS_ZCMT,	/* zcmt only */
+  CSR_CLASS_ZICFISS,	/* Zicfiss */
   CSR_CLASS_V,		/* rvv only */
   CSR_CLASS_DEBUG,	/* debug CSR */
   CSR_CLASS_H,		/* hypervisor */
@@ -1076,6 +1077,9 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_ZCMT:
       extension = "zcmt";
       break;
+    case CSR_CLASS_ZICFISS:
+      extension = "zicfiss";
+      break;
     case CSR_CLASS_V:
       extension = "zve32x";
       break;
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index a1d1147..572f76c 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -408,6 +408,7 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4447 \(sctrdepth\) at cfa\+1404
   DW_CFA_offset_extended_sf: r4686 \(vsctrctl\) at cfa\+2360
   DW_CFA_offset_extended_sf: r4942 \(mctrctl\) at cfa\+3384
+  DW_CFA_offset_extended_sf: r4113 \(ssp\) at cfa\+324
   DW_CFA_offset_extended: r4096 \(ustatus\) at cfa\+0
   DW_CFA_offset_extended_sf: r4100 \(uie\) at cfa\+16
   DW_CFA_offset_extended_sf: r4101 \(utvec\) at cfa\+20
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index 7b9d663..68b3406 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -411,6 +411,8 @@ _start:
 	.cfi_offset sctrdepth, 1404
 	.cfi_offset vsctrctl, 2360
 	.cfi_offset mctrctl, 3384
+	# Zicfiss extension
+	.cfi_offset ssp, 324
 	# dropped
 	.cfi_offset ustatus, 0
 	.cfi_offset uie, 16
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index 75027b2..0729795 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -735,6 +735,8 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+21459073[ 	]+csrw[ 	]+vsieh,a1
 [ 	]+[0-9a-f]+:[ 	]+25402573[ 	]+csrr[ 	]+a0,vsiph
 [ 	]+[0-9a-f]+:[ 	]+25459073[ 	]+csrw[ 	]+vsiph,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
 [ 	]+[0-9a-f]+:[ 	]+15002573[ 	]+csrr[ 	]+a0,siselect
 [ 	]+[0-9a-f]+:[ 	]+15059073[ 	]+csrw[ 	]+siselect,a1
 [ 	]+[0-9a-f]+:[ 	]+15102573[ 	]+csrr[ 	]+a0,sireg
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 30c5600..2427ba9 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1285,6 +1285,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 9726721..70cafb8 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -735,6 +735,8 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+21459073[ 	]+csrw[ 	]+vsieh,a1
 [ 	]+[0-9a-f]+:[ 	]+25402573[ 	]+csrr[ 	]+a0,vsiph
 [ 	]+[0-9a-f]+:[ 	]+25459073[ 	]+csrw[ 	]+vsiph,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
 [ 	]+[0-9a-f]+:[ 	]+15002573[ 	]+csrr[ 	]+a0,siselect
 [ 	]+[0-9a-f]+:[ 	]+15059073[ 	]+csrw[ 	]+siselect,a1
 [ 	]+[0-9a-f]+:[ 	]+15102573[ 	]+csrr[ 	]+a0,sireg
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 27efda1..aeec089 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1281,6 +1281,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 41b6b3e..daf79f4 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -735,6 +735,8 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+21459073[ 	]+csrw[ 	]+vsieh,a1
 [ 	]+[0-9a-f]+:[ 	]+25402573[ 	]+csrr[ 	]+a0,vsiph
 [ 	]+[0-9a-f]+:[ 	]+25459073[ 	]+csrw[ 	]+vsiph,a1
+[ 	]+[0-9a-f]+:[ 	]+01102573[ 	]+csrr[ 	]+a0,ssp
+[ 	]+[0-9a-f]+:[ 	]+01159073[ 	]+csrw[ 	]+ssp,a1
 [ 	]+[0-9a-f]+:[ 	]+15002573[ 	]+csrr[ 	]+a0,siselect
 [ 	]+[0-9a-f]+:[ 	]+15059073[ 	]+csrw[ 	]+siselect,a1
 [ 	]+[0-9a-f]+:[ 	]+15102573[ 	]+csrr[ 	]+a0,sireg
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index d9049c1..3710da9 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1005,6 +1005,10 @@
 .*Info: macro .*
 .*Warning: invalid CSR `vsiph', needs `ssaia' extension
 .*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
+.*Warning: invalid CSR `ssp', needs `zicfiss' extension
+.*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
 .*Info: macro .*
 .*Warning: invalid CSR `siselect', needs `ssaia or sscsrind' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index fca0728..44fc1e7 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -416,6 +416,9 @@
 	csr vsieh
 	csr vsiph
 
+	# Zicfiss
+	csr ssp
+
 	# Sscsrind
 	csr siselect
 	csr sireg
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 8337bd3..529910d 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -48,6 +48,8 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zca1p0_zcmp1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zca1p0_zcmop1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicfilp1p0_zicsr2p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index 2ef14ab..88ade91 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -53,6 +53,9 @@ imply zcf
 imply zcmp
 imply zcmop
 
+imply zicfilp
+imply zicfiss
+
 imply shcounterenw
 imply shgatpa
 imply shtvala
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 981679b..f92c98f 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -26,6 +26,8 @@ All available -march extensions for RISC-V:
 	zihintpause                             2.0
 	zihpm                                   2.0
 	zimop                                   1.0
+	zicfiss                                 1.0
+	zicfilp                                 1.0
 	zmmul                                   1.0
 	za64rs                                  1.0
 	za128rs                                 1.0
diff --git a/gas/testsuite/gas/riscv/zicfisslp-32.d b/gas/testsuite/gas/riscv/zicfisslp-32.d
new file mode 100644
index 0000000..360dc0c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfisslp-32.d
@@ -0,0 +1,27 @@
+#as: -march=rv32gc_zicfiss_zicfilp
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ce104073[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+ce504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+cdc0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+cdc2c073[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+cdc04573[ 	]+ssrdp[ 	]+a0
+[ 	]+[0-9a-f]+:[ 	]+48a5252f[ 	]+ssamoswap.w[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+48a5252f[ 	]+ssamoswap.w[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ca5252f[ 	]+ssamoswap.w.aq[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ca5252f[ 	]+ssamoswap.w.aq[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4aa5252f[ 	]+ssamoswap.w.rl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4aa5252f[ 	]+ssamoswap.w.rl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ea5252f[ 	]+ssamoswap.w.aqrl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ea5252f[ 	]+ssamoswap.w.aqrl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+00111017[ 	]+lpad[ 	]+0x111
diff --git a/gas/testsuite/gas/riscv/zicfisslp-32.s b/gas/testsuite/gas/riscv/zicfisslp-32.s
new file mode 100644
index 0000000..bd61161
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfisslp-32.s
@@ -0,0 +1,32 @@
+	# Zicfiss
+.option push
+.option arch, rv32i_zicfiss
+	sspush x1
+	sspush x5
+	sspopchk x1
+	sspopchk x5
+	ssrdp a0
+	ssamoswap.w     a0,a0,(a0)
+	ssamoswap.w     a0,a0,0(a0)
+	ssamoswap.w.aq  a0,a0,(a0)
+	ssamoswap.w.aq  a0,a0,0(a0)
+	ssamoswap.w.rl  a0,a0,(a0)
+	ssamoswap.w.rl  a0,a0,0(a0)
+	ssamoswap.w.aqrl	a0,a0,(a0)
+	ssamoswap.w.aqrl	a0,a0,0(a0)
+.option pop
+
+	# Zicfiss and Zcmop
+.option push
+.option arch, rv32ic_zicfiss_zcmop
+	sspush x1
+	c.sspush x1
+	sspopchk x5
+	c.sspopchk x5
+.option pop
+
+	# Zicfilp
+.option push
+.option arch, rv32ic_zicfilp
+	lpad 0x111
+.option pop
diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.d b/gas/testsuite/gas/riscv/zicfisslp-64.d
new file mode 100644
index 0000000..0eb1b87
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.d
@@ -0,0 +1,27 @@
+#as: -march=rv64gc_zicfiss_zicfilp
+#objdump: -dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ce104073[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+ce504073[ 	]+sspush[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+cdc0c073[ 	]+sspopchk[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+cdc2c073[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+cdc04573[ 	]+ssrdp[ 	]+a0
+[ 	]+[0-9a-f]+:[ 	]+48a5352f[ 	]+ssamoswap.d[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+48a5352f[ 	]+ssamoswap.d[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ca5352f[ 	]+ssamoswap.d.aq[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ca5352f[ 	]+ssamoswap.d.aq[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4aa5352f[ 	]+ssamoswap.d.rl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4aa5352f[ 	]+ssamoswap.d.rl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ea5352f[ 	]+ssamoswap.d.aqrl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+4ea5352f[ 	]+ssamoswap.d.aqrl[ 	]+a0,a0,\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+sspush[ 	]+ra
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+sspopchk[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+00111017[ 	]+lpad[ 	]+0x111
diff --git a/gas/testsuite/gas/riscv/zicfisslp-64.s b/gas/testsuite/gas/riscv/zicfisslp-64.s
new file mode 100644
index 0000000..1199a43
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicfisslp-64.s
@@ -0,0 +1,32 @@
+	# Zicfiss
+.option push
+.option arch, rv64i_zicfiss
+	sspush x1
+	sspush x5
+	sspopchk x1
+	sspopchk x5
+	ssrdp a0
+	ssamoswap.d       a0, a0, 0(a0)
+	ssamoswap.d       a0, a0, (a0)
+	ssamoswap.d.aq    a0, a0, 0(a0)
+	ssamoswap.d.aq    a0, a0, (a0)
+	ssamoswap.d.rl    a0, a0, 0(a0)
+	ssamoswap.d.rl    a0, a0, (a0)
+	ssamoswap.d.aqrl  a0, a0, 0(a0)
+	ssamoswap.d.aqrl  a0, a0, (a0)
+.option pop
+
+	# Zicfiss and Zcmop
+.option push
+.option arch, rv64ic_zicfiss_zcmop
+	sspush x1
+	c.sspush x1
+	sspopchk x5
+	c.sspopchk x5
+.option pop
+
+	# Zicfilp
+.option push
+.option arch, rv64ic_zicfilp
+	lpad 0x111
+.option pop
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1696ac7..71ad7ff 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2353,6 +2353,24 @@
 #define MASK_HSV_W 0xfe007fff
 #define MATCH_HSV_D 0x6e004073
 #define MASK_HSV_D 0xfe007fff
+/* Zicfiss instructions.  */
+#define MATCH_SSPUSH 0xce004073
+#define MASK_SSPUSH 0xfe0fffff
+#define MATCH_SSPOPCHK 0xcdc04073
+#define MASK_SSPOPCHK 0xfff07fff
+#define MATCH_SSRDP 0xcdc04073
+#define MASK_SSRDP 0xfffff07f
+#define MATCH_SSAMOSWAP_W 0x4800202f
+#define MASK_SSAMOSWAP_W 0xf800707f
+#define MATCH_SSAMOSWAP_D 0x4800302f
+#define MASK_SSAMOSWAP_D 0xf800707f
+#define MATCH_C_SSPUSH 0x6081
+#define MASK_C_SSPUSH 0xffff
+#define MATCH_C_SSPOPCHK 0x6281
+#define MASK_C_SSPOPCHK 0xffff
+/* Zicfilp instructions.  */
+#define MATCH_LPAD 0x17
+#define MASK_LPAD  0xfff
 /* Zicbop hint instructions. */
 #define MATCH_PREFETCH_I 0x6013
 #define MASK_PREFETCH_I 0x1f07fff
@@ -4203,6 +4221,8 @@
 #define CSR_SCTRDEPTH 0x15f
 #define CSR_VSCTRCTL 0x24e
 #define CSR_MCTRCTL 0x34e
+/* Zicfissp CSR addresses.  */
+#define CSR_SSP 0x11
 /* Unprivileged Floating-Point CSR addresses.  */
 #define CSR_FFLAGS 0x1
 #define CSR_FRM 0x2
@@ -4892,6 +4912,17 @@ DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S)
 /* XVentanaCondOps instructions. */
 DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
 DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
+
+/* Zicfiss instructions.  */
+DECLARE_INSN(sspush, MATCH_SSPUSH, MASK_SSPUSH)
+DECLARE_INSN(sspopchk, MATCH_SSPOPCHK, MASK_SSPOPCHK)
+DECLARE_INSN(c_sspush, MATCH_C_SSPUSH, MASK_C_SSPUSH)
+DECLARE_INSN(c_sspopchk, MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK)
+DECLARE_INSN(ssrdp, MATCH_SSRDP, MASK_SSRDP)
+DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W)
+DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D)
+/* Zicfilp instructions.  */
+DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD)
 #endif /* DECLARE_INSN */
 #ifdef DECLARE_CSR
 /* Unprivileged Counter/Timers CSRs.  */
@@ -5318,6 +5349,8 @@ DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, P
 DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Zicfiss CSRs.  */
+DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZICFISS, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Dropped CSRs.  */
 DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12)
 DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index e7d2d78..6bcea63 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -515,6 +515,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
+  INSN_CLASS_ZICFISS,
+  INSN_CLASS_ZICFISS_AND_ZCMOP,
+  INSN_CLASS_ZICFILP,
   INSN_CLASS_ZCB,
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 31f96ab..ed37eb7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -391,6 +391,30 @@ match_cm_jalt (const struct riscv_opcode *op, insn_t insn)
    Because of the lookup algorithm used, entries with the same opcode
    name must be contiguous.  */
 
+static int
+match_rs1_x1x5_opcode (const struct riscv_opcode *op,
+		       insn_t insn)
+{
+  int rs1 = (insn & MASK_RS1) >> OP_SH_RS1;
+  return match_opcode (op, insn) && (rs1 == 1 || rs1 == 5);
+}
+
+static int
+match_rs2_x1x5_opcode (const struct riscv_opcode *op,
+		       insn_t insn)
+{
+  int rs2 = (insn & MASK_RS2) >> OP_SH_RS2;
+  return match_opcode (op, insn) && (rs2 == 1 || rs2 == 5);
+}
+
+static int
+match_rd_x1x5_opcode (const struct riscv_opcode *op,
+		      insn_t insn)
+{
+  int rd = (insn & MASK_RD) >> OP_SH_RD;
+  return match_opcode (op, insn) && (rd == 1 || rd == 5);
+}
+
 const struct riscv_opcode riscv_opcodes[] =
 {
 /* name, xlen, isa, operands, match, mask, match_func, pinfo.  */
@@ -546,6 +570,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"or",          0, INSN_CLASS_C, "Cs,Cw,Ct",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
 {"or",          0, INSN_CLASS_C, "Cs,Ct,Cw",  MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS },
 {"or",          0, INSN_CLASS_I, "d,s,t",     MATCH_OR, MASK_OR, match_opcode, 0 },
+
+/* Zicfilp instructions.  */
+{"lpad",        0, INSN_CLASS_ZICFILP, "u",   MATCH_LPAD, MASK_LPAD, match_opcode, 0 },
+
 {"auipc",       0, INSN_CLASS_I, "d,u",       MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 },
 {"seqz",        0, INSN_CLASS_I, "d,s",       MATCH_SLTIU|ENCODE_ITYPE_IMM (1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS },
 {"snez",        0, INSN_CLASS_I, "d,t",       MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
@@ -1150,6 +1178,23 @@ const struct riscv_opcode riscv_opcodes[] =
 {"czero.eqz",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
 {"czero.nez",  0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
 
+/* Zicfiss instructions.  */
+{"sspush",            0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, INSN_ALIAS },
+{"sspush",            0, INSN_CLASS_ZICFISS,           "t", MATCH_SSPUSH, MASK_SSPUSH, match_rs2_x1x5_opcode, 0 },
+{"sspopchk",          0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, INSN_ALIAS },
+{"sspopchk",          0, INSN_CLASS_ZICFISS,           "s", MATCH_SSPOPCHK, MASK_SSPOPCHK, match_rs1_x1x5_opcode, 0 },
+{"c.sspush",          0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPUSH, MASK_C_SSPUSH, match_rd_x1x5_opcode, 0 },
+{"c.sspopchk",        0, INSN_CLASS_ZICFISS_AND_ZCMOP, "d", MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK, match_rd_x1x5_opcode, 0 },
+{"ssrdp",             0, INSN_CLASS_ZICFISS,           "d", MATCH_SSRDP, MASK_SSRDP, match_opcode, 0 },
+{"ssamoswap.w",      32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aq",   32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQ, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.rl",   32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_RL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.w.aqrl", 32, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_W|MASK_AQRL, MASK_SSAMOSWAP_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ssamoswap.d",      64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"ssamoswap.d.aq",   64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQ, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"ssamoswap.d.rl",   64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_RL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"ssamoswap.d.aqrl", 64, INSN_CLASS_ZICFISS,    "d,t,0(s)", MATCH_SSAMOSWAP_D|MASK_AQRL, MASK_SSAMOSWAP_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+
 /* Zimop instructions.  */
 {"mop.r.0",    0, INSN_CLASS_ZIMOP, "d,s",    MATCH_MOP_R_0,  MASK_MOP_R_0,  match_opcode, 0 },
 {"mop.r.1",    0, INSN_CLASS_ZIMOP, "d,s",    MATCH_MOP_R_1,  MASK_MOP_R_1,  match_opcode, 0 },