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-rw-r--r--opcodes/i386-dis-evex.h8
-rw-r--r--opcodes/i386-dis.c14
-rw-r--r--opcodes/i386-gen.c3
-rw-r--r--opcodes/i386-opc.h5
-rw-r--r--opcodes/i386-opc.tbl14
5 files changed, 30 insertions, 14 deletions
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index e72c472..ef5c963 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -662,7 +662,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A42) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A43) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A44) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2779,6 +2779,12 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3A43_P_2) },
},
+ /* PREFIX_EVEX_0F3A44 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpclmulqdq", { XM, Vex, EXx, Ib }, 0 },
+ },
/* PREFIX_EVEX_0F3A50 */
{
{ Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index fe9fcd9..7f3b18f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1701,6 +1701,7 @@ enum
PREFIX_EVEX_0F3A3F,
PREFIX_EVEX_0F3A42,
PREFIX_EVEX_0F3A43,
+ PREFIX_EVEX_0F3A44,
PREFIX_EVEX_0F3A50,
PREFIX_EVEX_0F3A51,
PREFIX_EVEX_0F3A54,
@@ -1902,7 +1903,6 @@ enum
VEX_LEN_0F3A38_P_2,
VEX_LEN_0F3A39_P_2,
VEX_LEN_0F3A41_P_2,
- VEX_LEN_0F3A44_P_2,
VEX_LEN_0F3A46_P_2,
VEX_LEN_0F3A60_P_2,
VEX_LEN_0F3A61_P_2,
@@ -2220,7 +2220,6 @@ enum
VEX_W_0F3A40_P_2,
VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2,
- VEX_W_0F3A44_P_2,
VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
@@ -6693,7 +6692,7 @@ static const struct dis386 prefix_table[][4] = {
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
+ { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
},
/* PREFIX_VEX_0F3A46 */
@@ -10110,11 +10109,6 @@ static const struct dis386 vex_len_table[][2] = {
{ VEX_W_TABLE (VEX_W_0F3A41_P_2) },
},
- /* VEX_LEN_0F3A44_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
- },
-
/* VEX_LEN_0F3A46_P_2 */
{
{ Bad_Opcode },
@@ -11429,10 +11423,6 @@ static const struct dis386 vex_w_table[][2] = {
{ "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
{
- /* VEX_W_0F3A44_P_2 */
- { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
- },
- {
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
},
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 47a9ddb..c04b364 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -271,6 +271,8 @@ static initializer cpu_flag_init[] =
"CpuGFNI" },
{ "CPU_VAES_FLAGS",
"CpuVAES" },
+ { "CPU_VPCLMULQDQ_FLAGS",
+ "CpuVPCLMULQDQ" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@@ -538,6 +540,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuCET),
BITFIELD (CpuGFNI),
BITFIELD (CpuVAES),
+ BITFIELD (CpuVPCLMULQDQ),
BITFIELD (CpuRegMMX),
BITFIELD (CpuRegXMM),
BITFIELD (CpuRegYMM),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c6c3f66..a14f66d 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -216,6 +216,8 @@ enum
CpuGFNI,
/* VAES instructions required */
CpuVAES,
+ /* VPCLMULQDQ instructions required */
+ CpuVPCLMULQDQ,
/* MMX register support required */
CpuRegMMX,
/* XMM register support required */
@@ -241,7 +243,7 @@ enum
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define CpuUnused (CpuMax + 1)
+ #define CpuUnused (CpuMax + 1)
/* We can check if an instruction is available with array instead
of bitfield. */
@@ -341,6 +343,7 @@ typedef union i386_cpu_flags
unsigned int cpucet:1;
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
+ unsigned int cpuvpclmulqdq:1;
unsigned int cpuregmmx:1;
unsigned int cpuregxmm:1;
unsigned int cpuregymm:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1511bdc..0dcc17b 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3122,6 +3122,12 @@ sha256rnds2, 2, 0xf38cb, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lS
sha256msg1, 2, 0xf38cc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
sha256msg2, 2, 0xf38cd, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
+// VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
+
+// VPCLMULQDQ instructions end
+
// AVX512F instructions.
kandnw, 3, 0x42, None, 1, CpuAVX512F, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
@@ -6102,6 +6108,14 @@ vaesenclast, 3, 0x66dd, None, 1, CpuVAES|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|V
// AVX512 + VAES instructions end
+// AVX512 + VPCLMULQDQ instructions
+
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|EVex=1|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=2|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
+vpclmulqdq, 4, 0x6644, None, 1, CpuVPCLMULQDQ|CpuAVX512VL, Modrm|EVex=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
+
+// AVX512 + VPCLMULQDQ instructions end
+
// CLZERO instructions
clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
generated by cgit v1.1 at 2025-02-06 10:56:28 +0000