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-rw-r--r--opcodes/aarch64-asm-2.c83
-rw-r--r--opcodes/aarch64-asm.c1
-rw-r--r--opcodes/aarch64-dis-2.c150
-rw-r--r--opcodes/aarch64-dis.c6
-rw-r--r--opcodes/aarch64-opc-2.c3
-rw-r--r--opcodes/aarch64-opc.c30
-rw-r--r--opcodes/aarch64-opc.h2
-rw-r--r--opcodes/aarch64-tbl.h33
8 files changed, 208 insertions, 100 deletions
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 6c58452..8bd9816 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -679,19 +679,19 @@ aarch64_insert_operand (const aarch64_operand *self,
case 226:
case 237:
case 241:
- case 245:
- case 252:
- case 253:
- case 260:
- case 261:
+ case 246:
+ case 254:
+ case 255:
case 262:
case 263:
+ case 264:
+ case 265:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 295:
case 297:
+ case 300:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -705,7 +705,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 299:
+ case 302:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
case 40:
@@ -713,10 +713,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 227:
case 228:
case 231:
- case 264:
- case 265:
- case 280:
- case 281:
+ case 266:
+ case 267:
case 282:
case 283:
case 284:
@@ -728,6 +726,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -776,13 +776,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 207:
case 208:
case 209:
- case 266:
- case 293:
- case 294:
+ case 268:
+ case 295:
case 296:
case 298:
- case 303:
- case 304:
+ case 299:
+ case 301:
+ case 306:
+ case 307:
return aarch64_ins_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -930,7 +931,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 199:
case 200:
case 201:
- case 279:
+ case 281:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 214:
case 215:
@@ -956,55 +957,57 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 240:
case 242:
- case 259:
- case 305:
- case 306:
- case 307:
+ case 261:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 243:
case 244:
- case 246:
case 247:
case 248:
case 249:
- case 258:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
+ case 260:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 245:
+ case 252:
+ case 253:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
case 256:
- case 267:
+ case 258:
+ case 269:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 255:
case 257:
+ case 259:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 268:
- case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 276:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 277:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 278:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 279:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 280:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
- case 302:
+ case 303:
+ case 304:
+ case 305:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 308:
- case 309:
- case 310:
case 311:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
+ case 313:
+ case 314:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 315:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 5c6a311..57fb861 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -2145,6 +2145,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
break;
case sme_size_12_bhs:
+ case sme_size_12_b:
insert_field (FLD_SME_size_12, &inst->value,
aarch64_get_variant (inst), 0);
break;
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 3d17f18..fd19b2d 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -204,32 +204,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00x101xx0xxxxxxxxxxxxxx
- luti4. */
- return 2671;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x000101x00xxxxxxxxxxxxxx
+ luti4. */
+ return 3394;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x000101x10xxxxxxxxxxxxxx
+ luti4. */
+ return 2671;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x000101xx1xxxxxxxxxxxxxx
+ luti4. */
+ return 2670;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000x00x101xx1xxxxxxxxxxxxxx
+ x1000000x100101xxxxxxxxxxxxxxxxx
luti4. */
- return 2670;
+ return 2669;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000x10x101xxxxxxxxxxxxxxxxx
+ x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 2669;
+ return 3395;
}
}
}
@@ -328,21 +350,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000010x110xxxxx00xxxxxxxxxx
- movt. */
- return 2689;
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010x1100xxxx00xxxxxxxxxx
+ movt. */
+ return 2689;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000010x1110xxxx00xxxxxxxxxx
+ movt. */
+ return 2688;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000010x111xxxxx00xxxxxxxxxx
+ x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 2688;
+ return 3396;
}
}
else
@@ -33676,19 +33709,19 @@ aarch64_extract_operand (const aarch64_operand *self,
case 226:
case 237:
case 241:
- case 245:
- case 252:
- case 253:
- case 260:
- case 261:
+ case 246:
+ case 254:
+ case 255:
case 262:
case 263:
+ case 264:
+ case 265:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 118:
case 119:
- case 295:
case 297:
+ case 300:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33707,7 +33740,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 299:
+ case 302:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 39:
case 40:
@@ -33715,10 +33748,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 227:
case 228:
case 231:
- case 264:
- case 265:
- case 280:
- case 281:
+ case 266:
+ case 267:
case 282:
case 283:
case 284:
@@ -33730,6 +33761,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 42:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -33779,13 +33812,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 207:
case 208:
case 209:
- case 266:
- case 293:
- case 294:
+ case 268:
+ case 295:
case 296:
case 298:
- case 303:
- case 304:
+ case 299:
+ case 301:
+ case 306:
+ case 307:
return aarch64_ext_imm (self, info, code, inst, errors);
case 51:
case 52:
@@ -33935,7 +33969,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 199:
case 200:
case 201:
- case 279:
+ case 281:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 214:
case 215:
@@ -33961,56 +33995,58 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 240:
case 242:
- case 259:
+ case 261:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 243:
case 244:
- case 246:
case 247:
case 248:
case 249:
- case 258:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
+ case 260:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case 245:
+ case 252:
+ case 253:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
case 256:
- case 267:
+ case 258:
+ case 269:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 255:
case 257:
+ case 259:
return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 268:
- case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 276:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 277:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 278:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 279:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 280:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
- case 302:
- return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 303:
+ case 304:
case 305:
- case 306:
- case 307:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
+ return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
case 308:
case 309:
case 310:
+ return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 311:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
+ case 313:
+ case 314:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 315:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 213df61..045af49 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -3415,6 +3415,12 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant -= 1;
break;
+ case sme_size_12_b:
+ variant = extract_field (FLD_SME_size_12, inst->value, 0);
+ if (variant != 0)
+ return false;
+ break;
+
case sme_size_22:
variant = extract_field (FLD_SME_size_22, inst->value, 0);
break;
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 14dd96a..71f6824 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -269,10 +269,12 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZdnT, FLD_SME_Zdn2_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
@@ -321,6 +323,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX2_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ea278bf..b704673 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -258,7 +258,9 @@ const aarch64_field fields[] =
{ 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
+ { 4, 1 }, /* SME_ZdnT: upper bit of Zt, bit [4]. */
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
+ { 0, 2 }, /* SME_Zdn2_0: lower 2 bits of Zt, bits [1:0]. */
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
{ 16, 4 }, /* SME_Zm: Z0-Z15, bits [19:16]. */
{ 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */
@@ -1919,6 +1921,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
+ case AARCH64_OPND_SME_Znx2_BIT_INDEX:
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Zt2:
case AARCH64_OPND_SME_Zt3:
@@ -1934,6 +1937,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_SME_Zdnx4_STRIDED:
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
/* 2-register lists have a stride of 8 and 4-register lists
@@ -3153,6 +3157,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_SME_ZT0_INDEX2_12:
+ if (!value_in_range_p (opnd->imm.value, 0, 3))
+ {
+ set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 3);
+ return 0;
+ }
+ break;
+
default:
break;
}
@@ -3745,9 +3757,14 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
&& ((opnd->type != AARCH64_OPND_SME_Zt2)
&& (opnd->type != AARCH64_OPND_SME_Zt3)
&& (opnd->type != AARCH64_OPND_SME_Zt4)))
- snprintf (buf, size, "{%s-%s}%s",
- style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
- style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
+ if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
+ snprintf (buf, size, "{%s-%s}%s",
+ style_reg (styler, "%s%d", prefix, first_reg),
+ style_reg (styler, "%s%d", prefix, last_reg), tb);
+ else
+ snprintf (buf, size, "{%s-%s}%s",
+ style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
+ style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);
else
{
const int reg0 = first_reg;
@@ -4216,9 +4233,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Zdnx4_STRIDED:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
+ case AARCH64_OPND_SME_Znx2_BIT_INDEX:
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
@@ -4906,6 +4925,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s[%s]", style_reg (styler, "zt0"),
style_imm (styler, "%d", (int) opnd->imm.value));
break;
+ case AARCH64_OPND_SME_ZT0_INDEX2_12:
+ snprintf (buf, size, "%s[%s, %s]", style_reg (styler, "zt0"),
+ style_imm (styler, "%d", (int) opnd->imm.value),
+ style_sub_mnem (styler, "mul vl"));
+ break;
case AARCH64_OPND_SME_ZT0_LIST:
snprintf (buf, size, "{%s}", style_reg (styler, "zt0"));
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 9b734d6..8804e7c 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -62,7 +62,9 @@ enum aarch64_field_kind
FLD_SME_VL_13,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
+ FLD_SME_ZdnT,
FLD_SME_Zdn2,
+ FLD_SME_Zdn2_0,
FLD_SME_Zdn4,
FLD_SME_Zm,
FLD_SME_Zm2,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index bffb422..5876592 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1814,6 +1814,13 @@
{ \
QLF2(S_S,NIL), \
}
+/* e.g. movt ZT0{[<offs>, MUL VL]}, <Zt> */
+/* The second operand doesn't have a qualifier and
+ is checked separetely during encoding. */
+#define OP_SVE_SU_Q \
+{ \
+ QLF2(S_Q,NIL), \
+}
#define OP_SVE_SUS \
{ \
QLF3(S_S,NIL,S_S), \
@@ -2050,6 +2057,13 @@
QLF3(S_S,NIL,W), \
QLF3(S_D,NIL,X), \
}
+/* e.g. luti4 { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn2> } */
+/* The second and third operands don't have qualifiers and
+ are checked separetely during encoding. */
+#define OP_SVE_VUU_B \
+{ \
+ QLF3(S_B,NIL,NIL), \
+}
#define OP_SVE_VUU_BHS \
{ \
QLF3(S_B,NIL,NIL), \
@@ -2752,6 +2766,8 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
AARCH64_FEATURES (2, LUT, SVE2);
static const aarch64_feature_set aarch64_feature_brbe =
AARCH64_FEATURE (BRBE);
+static const aarch64_feature_set aarch64_feature_sme_lutv2 =
+ AARCH64_FEATURES (3, SME_LUTv2, SME2, SME2p1);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2829,6 +2845,7 @@ static const aarch64_feature_set aarch64_feature_brbe =
#define LUT &aarch64_feature_lut
#define LUT_SVE2 &aarch64_feature_lut_sve2
#define BRBE &aarch64_feature_brbe
+#define LUTv2_SME2 &aarch64_feature_sme_lutv2
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3029,6 +3046,9 @@ static const aarch64_feature_set aarch64_feature_brbe =
FLAGS, CONSTRAINTS, 0, NULL }
#define BRBE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, ic_system, 0, BRBE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \
+ FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6615,6 +6635,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0),
LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0),
+ /* SME2 lutv2. */
+ LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
+ LUTv2_SME2_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
+ LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -7139,6 +7164,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_strided_reglist, "SME_Zdnx4_STRIDED", \
+ 4 << OPD_F_OD_LSB, F(FLD_SME_ZdnT, FLD_SME_Zdn2_0), \
+ "a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \
"an SVE vector register") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
@@ -7147,6 +7175,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SME_Zm4), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
F(FLD_SME_Zn2), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2_BIT_INDEX", \
+ 2 << OPD_F_OD_LSB, F(FLD_SME_Zn2), \
+ "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zn4), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
@@ -7257,6 +7288,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \
Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \
F (FLD_imm3_12), "a ZT0 index") \
+ Y(IMMEDIATE, imm, "SME_ZT0_INDEX2_12", 0, \
+ F (FLD_imm3_12), "a ZT0 index") \
Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
"a 16-bit unsigned immediate for TME tcancel") \
generated by cgit v1.1 at 2024-11-15 17:15:23 +0000