diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 10 | ||||
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 32 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 16 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.h | 16 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 32 |
6 files changed, 55 insertions, 55 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 73ee15a..7351c24 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -120,7 +120,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ assert (info->idx == 1); /* Vn */ aarch64_insn value = info->reglane.index << pos; - insert_field (FLD_imm4, code, value, 0); + insert_field (FLD_imm4_11, code, value, 0); } else { @@ -962,7 +962,7 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, insert_field (FLD_shift, code, aarch64_get_operand_modifier_value (info->shifter.kind), 0); /* imm6 */ - insert_field (FLD_imm6, code, info->shifter.amount, 0); + insert_field (FLD_imm6_10, code, info->shifter.amount, 0); return true; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index ddbeefa..05e285f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -335,7 +335,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, unsigned shift; /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ assert (info->idx == 1); /* Vn */ - aarch64_insn value = extract_field (FLD_imm4, code, 0); + aarch64_insn value = extract_field (FLD_imm4_11, code, 0); /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ info->qualifier = get_expected_qualifier (inst, info->idx); shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -1430,7 +1430,7 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, instructions. */ return false; /* imm6 */ - info->shifter.amount = extract_field (FLD_imm6, code, 0); + info->shifter.amount = extract_field (FLD_imm6_10, code, 0); /* This makes the constraint checking happy. */ info->shifter.operator_present = 1; @@ -1838,7 +1838,7 @@ aarch64_ext_sme_za_list (const aarch64_operand *self, } /* Decode ZA array vector select register (Rv field), optional vector and - memory offset (imm4 field). + memory offset (imm4_11 field). */ bool aarch64_ext_sme_za_array (const aarch64_operand *self, @@ -2669,7 +2669,7 @@ convert_csinc_to_cset (aarch64_inst *inst) /* MOV <Wd>, #<imm> is equivalent to: - MOVZ <Wd>, #<imm16>, LSL #<shift>. + MOVZ <Wd>, #<imm16_5>, LSL #<shift>. A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when ORR has an immediate that could be generated by a MOVZ or MOVN instruction, @@ -2956,7 +2956,7 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) switch (inst->opcode->iclass) { case sme_mov: - variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10); + variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_22); if (variant >= 4 && variant < 7) return false; if (variant == 7) diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 2fa09b2..1d59a8b 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -66,8 +66,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4}, "an immediate as the index of the least significant byte"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_2}, "an immediate as the index of the least significant byte"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_11}, "an immediate as the index of the least significant byte"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_0}, "an immediate as the index of the least significant byte"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"}, @@ -78,25 +78,25 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"}, {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the leftmost bit number to be moved from the source"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "the width of the bit-field"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_2}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the leftmost bit number to be moved from the source"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the width of the bit-field"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_3}, "a 4-bit unsigned Logical Address Tag modifier"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_10}, "a 4-bit unsigned Logical Address Tag modifier"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"}, {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_2}, "a 16-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit immediate with optional left shift"}, {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"}, @@ -236,16 +236,16 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"}, - {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, - {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 7a88c19..46c49dd 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -239,11 +239,11 @@ const aarch64_field fields[] = { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */ { 22, 2 }, /* type: floating point type field in fp data inst. */ { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */ - { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */ - { 15, 6 }, /* imm6_2: in rmif instructions. */ - { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */ - { 0, 4 }, /* imm4_2: in rmif instructions. */ - { 10, 4 }, /* imm4_3: in adddg/subg instructions. */ + { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */ + { 15, 6 }, /* imm6_15: in rmif instructions. */ + { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */ + { 0, 4 }, /* imm4_0: in rmif instructions. */ + { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */ @@ -251,8 +251,8 @@ const aarch64_field fields[] = { 12, 9 }, /* imm9: in load/store pre/post index instructions. */ { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ { 5, 14 }, /* imm14: in test bit and branch instructions. */ - { 5, 16 }, /* imm16: in exception instructions. */ - { 0, 16 }, /* imm16_2: in udf instruction. */ + { 5, 16 }, /* imm16_5: in exception instructions. */ + { 0, 16 }, /* imm16_0: in udf instruction. */ { 0, 26 }, /* imm26: in unconditional branch instructions. */ { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */ { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */ @@ -326,7 +326,7 @@ const aarch64_field fields[] = { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ - { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */ + { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 2bbc81e..fc1f808 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -66,11 +66,11 @@ enum aarch64_field_kind FLD_shift, FLD_type, FLD_ldst_size, - FLD_imm6, - FLD_imm6_2, - FLD_imm4, - FLD_imm4_2, - FLD_imm4_3, + FLD_imm6_10, + FLD_imm6_15, + FLD_imm4_11, + FLD_imm4_0, + FLD_imm4_10, FLD_imm4_5, FLD_imm5, FLD_imm7, @@ -78,8 +78,8 @@ enum aarch64_field_kind FLD_imm9, FLD_imm12, FLD_imm14, - FLD_imm16, - FLD_imm16_2, + FLD_imm16_5, + FLD_imm16_0, FLD_imm26, FLD_imms, FLD_immr, @@ -153,7 +153,7 @@ enum aarch64_field_kind FLD_SVE_xs_22, FLD_SME_ZAda_2b, FLD_SME_ZAda_3b, - FLD_SME_size_10, + FLD_SME_size_22, FLD_SME_Q, FLD_SME_V, FLD_SME_Rv, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 8deeded..82f4af2 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5535,9 +5535,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 4-bit opcode field named for historical reasons C0 - C15") \ Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \ "a 4-bit opcode field named for historical reasons C0 - C15") \ - Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \ + Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4_11), \ "an immediate as the index of the least significant byte") \ - Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_2), \ + Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_0), \ "an immediate as the index of the least significant byte") \ Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ "a left shift amount for an AdvSIMD register") \ @@ -5557,19 +5557,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an 8-bit floating-point constant") \ Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ "the right rotate amount") \ - Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \ + Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6_10), \ "the leftmost bit number to be moved from the source") \ - Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \ + Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6_10), \ "the width of the bit-field") \ - Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \ - Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_2), "an immediate") \ + Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6_10), "an immediate") \ + Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_15), "an immediate") \ Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ "a 3-bit unsigned immediate") \ Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ "a 3-bit unsigned immediate") \ Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ "a 4-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \ + Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_10), \ "a 4-bit unsigned Logical Address Tag modifier") \ Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ "a 7-bit unsigned immediate") \ @@ -5577,9 +5577,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 10-bit unsigned multiple of 16") \ Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ "the bit number to be tested") \ - Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ + Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16_5), \ "a 16-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \ + Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_0), \ "a 16-bit unsigned immediate") \ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ "a 5-bit unsigned immediate") \ @@ -5591,7 +5591,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "Logical immediate") \ Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ "a 12-bit unsigned immediate with optional left shift of 12 bits")\ - Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \ + Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16_5), \ "a 16-bit immediate with optional left shift") \ Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ "the number of bits after the binary point in the fixed-point value")\ @@ -5909,28 +5909,28 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ "an SME ZA tile ZA0-ZA7") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ - F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ + F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ - F(FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \ + F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ - F(FLD_SME_size_10,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2), \ + F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0, \ - F(FLD_SME_Rv,FLD_imm4_2), "ZA array") \ + F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_imm4_2), "memory offset") \ + F(FLD_Rn,FLD_imm4_0), "memory offset") \ Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ F(FLD_CRm), "streaming mode") \ Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ - Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ "an indexed SM3 vector immediate") \ |