diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2015-05-21 23:16:45 +0800 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-02-04 19:02:19 -0500 |
| commit | b9249c461c72b35dd9b6f274406c336f6a68ae98 (patch) | |
| tree | 2f2314445c8c95e8dc1c3c8de6d824e9042b15fe /sim/riscv/model_list.def | |
| parent | a9ab6e2ea07829d89b97d1f47ecb524c251252e7 (diff) | |
| download | binutils-b9249c461c72b35dd9b6f274406c336f6a68ae98.zip binutils-b9249c461c72b35dd9b6f274406c336f6a68ae98.tar.gz binutils-b9249c461c72b35dd9b6f274406c336f6a68ae98.tar.bz2 | |
sim: riscv: new port
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions. It also
covers 32-bit & 64-bit targets.
The unittest coverage is a bit weak atm, but should get better.
Diffstat (limited to 'sim/riscv/model_list.def')
| -rw-r--r-- | sim/riscv/model_list.def | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def new file mode 100644 index 0000000..5efd85a --- /dev/null +++ b/sim/riscv/model_list.def @@ -0,0 +1,9 @@ +M(G) +M(I) +M(IM) +M(IMA) +M(IA) +M(E) +M(EM) +M(EMA) +M(EA) |