From b9249c461c72b35dd9b6f274406c336f6a68ae98 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Thu, 21 May 2015 23:16:45 +0800
Subject: sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
---
 sim/riscv/model_list.def | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 sim/riscv/model_list.def

(limited to 'sim/riscv/model_list.def')

diff --git a/sim/riscv/model_list.def b/sim/riscv/model_list.def
new file mode 100644
index 0000000..5efd85a
--- /dev/null
+++ b/sim/riscv/model_list.def
@@ -0,0 +1,9 @@
+M(G)
+M(I)
+M(IM)
+M(IMA)
+M(IA)
+M(E)
+M(EM)
+M(EMA)
+M(EA)
-- 
cgit v1.1

