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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-27 00:10:58 +0000 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-09-02 09:40:04 +0800 |
| commit | e9f7ba21f08a264f813140eb6221e9d9670dc12f (patch) | |
| tree | da6e290e6ecd9ee120d1e87acbc3a2a877252f60 /opcodes | |
| parent | 5edf42b635a375f7bf79e2079529eeb869129cbe (diff) | |
| download | binutils-e9f7ba21f08a264f813140eb6221e9d9670dc12f.zip binutils-e9f7ba21f08a264f813140eb6221e9d9670dc12f.tar.gz binutils-e9f7ba21f08a264f813140eb6221e9d9670dc12f.tar.bz2 | |
RISC-V: Add address printer tests with ADDIW
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
Diffstat (limited to 'opcodes')
0 files changed, 0 insertions, 0 deletions