diff options
| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-04 14:06:38 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-15 13:11:48 +0000 |
| commit | e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba (patch) | |
| tree | 01d2911ac905de462246f50d060ea75c2ac03edc /opcodes | |
| parent | b88fbd5213b2c38141c066365d7ea092ab7cfea8 (diff) | |
| download | binutils-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.zip binutils-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.tar.gz binutils-e771eaf8bb4cfc4a04346a14756fa21e01e7b9ba.tar.bz2 | |
aarch64: rcpc3: Add integer load/store insns
Along with the relevant unit tests and updates to the existing
regression tests, this adds support for the following novel rcpc3
insns:
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>]
LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>]
LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16
STILP <Wt1>, <Wt2>, [<Xn|SP>]
STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
STILP <Xt1>, <Xt2>, [<Xn|SP>]
STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]!
LDAPR <Wt>, [<Xn|SP>], #4
LDAPR <Xt>, [<Xn|SP>], #8
STLR <Wt>, [<Xn|SP>, #-4]!
STLR <Xt>, [<Xn|SP>, #-8]!
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1b3895b..8855c83 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4216,6 +4216,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0), + /* RCPC3 extension. */ + RCPC3_INSN ("ldiapp", 0x19400800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_POSTIND), QL_R2NIL, F_RCPC3_SIZE), + RCPC3_INSN ("stilp", 0x19000800, 0x3fe0ec00, rcpc3, OP3 (Rt, Rs, RCPC3_ADDR_OPT_PREIND_WB), QL_R2NIL, F_RCPC3_SIZE), + RCPC3_INSN ("ldapr", 0x19c00800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_POSTIND), QL_R1NIL, F_RCPC3_SIZE), + RCPC3_INSN ("stlr", 0x19800800, 0x3ffffc00, rcpc3, OP2 (Rt, RCPC3_ADDR_PREIND_WB), QL_R1NIL, F_RCPC3_SIZE), /* Move wide (immediate). */ CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS), CORE_INSN ("mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV), |