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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:51 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:48 +0800 |
| commit | af38c6367ff0c6af1639b389eb34cf9983c30ff5 (patch) | |
| tree | 7669d1eabbe02ea5befdadbc0c3cee1666c83dd8 /opcodes | |
| parent | 42878336131e1b90623c5e2d7d011acc9b35c950 (diff) | |
| download | binutils-af38c6367ff0c6af1639b389eb34cf9983c30ff5.zip binutils-af38c6367ff0c6af1639b389eb34cf9983c30ff5.tar.gz binutils-af38c6367ff0c6af1639b389eb34cf9983c30ff5.tar.bz2 | |
RISC-V: Add support for Zfbfmin extension
This implements the Zfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts>
1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
FMV.H.X instructions as defined in the Zfh extension.
2 The Zfhmin extension includes the following instructions from the Zfh
extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>
3 Zfhmin extension depend on 'F'.
4 Simply put, just make Zfbfmin dependent on Zfhmin.
Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.
5 For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zfbfmin.d: New test.
* testsuite/gas/riscv/zfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
(MASK_FCVT_BF16_S): Ditto.
(MATCH_FCVT_S_BF16): Ditto.
(MASK_FCVT_S_BF16): Ditto.
(DECLARE_INSN): New declarations for Zfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.
opcodes/ChangeLog:
* riscv-opc.c: Add Zfbfmin instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 4bb54b7..1ccf068 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -829,6 +829,11 @@ const struct riscv_opcode riscv_opcodes[] = {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, +/* Zfbfmin instructions. */ +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, + /* Single-precision floating-point instruction subset. */ {"frcsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, {"frsr", 0, INSN_CLASS_F_INX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, |