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| author | Indu Bhagat <indu.bhagat@oracle.com> | 2024-01-15 01:00:42 -0800 |
|---|---|---|
| committer | Indu Bhagat <indu.bhagat@oracle.com> | 2024-01-15 03:31:35 -0800 |
| commit | 9f00e4b78e6b7d68ee9a0052a9553472982afc91 (patch) | |
| tree | 019b939e8627a7934ce6aba1467658d7a5fd4ea3 /opcodes | |
| parent | 9dd9781ab0457a59e8732fd71b91af1662c2ecff (diff) | |
| download | binutils-9f00e4b78e6b7d68ee9a0052a9553472982afc91.zip binutils-9f00e4b78e6b7d68ee9a0052a9553472982afc91.tar.gz binutils-9f00e4b78e6b7d68ee9a0052a9553472982afc91.tar.bz2 | |
opcodes: i386-reg.tbl: Add a comment to reflect dependency on ordering
The ginsn representation keeps the DWARF register number of the
operands. The API ginsn_dw2_regnum relies on the the relative ordering
of these register entries in the table. Add a comment to make it clear.
opcodes/
* i386-reg.tbl: Add a comment.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-reg.tbl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 5b80ee6..f923153 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -18,6 +18,9 @@ // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA // 02110-1301, USA. +// The code in gas backend for SCFI relies on the relative ordering +// of 8 bit / 16 bit / 32 bit / 64 bit regs + // 8 bit regs al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval |