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authorAndrew Haley <aph@redhat.com>2000-02-22 14:41:46 +0000
committerAndrew Haley <aph@redhat.com>2000-02-22 14:41:46 +0000
commit8027df8989e109409e2661cd9d963f7416f7aba2 (patch)
treeb883478236e4cc62f9dfcbe1487c331e448130d2 /opcodes
parent367c01aff994bc4ae31cdf92707ef91cad68abcf (diff)
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1999-12-30 Andrew Haley <aph@cygnus.com>
* mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: force gp32 to zero. * mips-opc.c (G6): New define. (mips_builtin_op): Add "move" definition for -gp32.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/mips-dis.c2
-rw-r--r--opcodes/mips-opc.c3
3 files changed, 11 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 396c80a..5602c5a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+1999-12-30 Andrew Haley <aph@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER:
+ force gp32 to zero.
+ * mips-opc.c (G6): New define.
+ (mips_builtin_op): Add "move" definition for -gp32.
+
2000-02-22 Ian Lance Taylor <ian@zembu.com>
From Grant Erickson <gerickso@Brocade.COM>:
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index a1bd62e..2e75266 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -388,7 +388,7 @@ _print_insn_mips (memaddr, word, info)
{
register const char *d;
- if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
+ if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
continue;
(*info->fprintf_func) (info->stream, "%s", op->name);
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index f81f44f..6cdd833 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -91,6 +91,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define G3 (I4 \
)
+#define G6 INSN_GP32
+
#define M1 0
#define M2 0
@@ -113,6 +115,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
+{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */