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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2016-07-13 01:42:28 -0700 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2016-07-13 16:05:40 +0200 |
| commit | 6e7ced37e756420742d51abb044c24d0f1929143 (patch) | |
| tree | 47b4f357fd3f938b6f5534db66d1c24d458fbad5 /opcodes | |
| parent | e87324746c45b0f2cd179ba59a80b43a435a9369 (diff) | |
| download | binutils-6e7ced37e756420742d51abb044c24d0f1929143.zip binutils-6e7ced37e756420742d51abb044c24d0f1929143.tar.gz binutils-6e7ced37e756420742d51abb044c24d0f1929143.tar.bz2 | |
opcodes,gas: support for the ldtxa SPARC instructions.
This patch adds support for the LDTXA instructions, along with the
corresponding ASIs. Tests for GAS are included.
opcodes/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (ldtxa): New macro.
(sparc_opcodes): Use the macro defined above to add entries for
the LDTXA instructions.
(asi_table): Add the ASI_TWINX_* asis used in the LDTXA
instruction.
gas/ChangeLog:
2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/ldtxa.s: New file.
* testsuite/gas/sparc/ldtxa.d: Likewise.
* testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/sparc-opc.c | 34 |
2 files changed, 42 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 56f33b5..091d8d4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> + + * sparc-opc.c (ldtxa): New macro. + (sparc_opcodes): Use the macro defined above to add entries for + the LDTXA instructions. + (asi_table): Add the ASI_TWINX_* asis used in the LDTXA + instruction. + 2016-07-07 James Bowman <james.bowman@ftdichip.com> * ft32-opc.c (ft32_opc_info): Correct mask for "callc" diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index ec44fb0..9d68223 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -370,6 +370,28 @@ const struct sparc_opcode sparc_opcodes[] = { { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, 0, v9 }, { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */ +/* Note that the LDTXA instructions share an opcode with the + (deprecated) LDTWA instructions below. They are differenciated by + the combination of the `i' instruction field and the ASI used in + the instruction. */ + +#define ldtxa(asi) \ +{ "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi)), "[1+2]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }, \ +{ "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi))|RS2_G0, "[1]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c } + +ldtxa (0x22), /* #ASI_TWINX_AIUP */ +ldtxa (0x23), /* #ASI_TWINX_AIUS */ +ldtxa (0x26), /* #ASI_TWINX_REAL */ +ldtxa (0x27), /* #ASI_TWINX_N */ +ldtxa (0x2A), /* #ASI_TWINX_AIUP_L */ +ldtxa (0x2B), /* #ASI_TWINX_AIUS_L */ +ldtxa (0x2E), /* #ASI_TWINX_REAL_L */ +ldtxa (0x2F), /* #ASI_TWINX_NL */ +ldtxa (0xE2), /* #ASI_TWINX_P */ +ldtxa (0xE3), /* #ASI_TWINX_S */ +ldtxa (0xEA), /* #ASI_TWINX_PL */ +ldtxa (0xEB), /* #ASI_TWINX_SL */ + { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9 }, { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */ { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9 }, @@ -2421,6 +2443,18 @@ static arg asi_table[] = { 0xf1, "#ASI_BLK_S", }, { 0xf8, "#ASI_BLK_PL", }, { 0xf9, "#ASI_BLK_SL", }, + { 0x22, "#ASI_TWINX_AIUP", }, + { 0x23, "#ASI_TWINX_AIUS", }, + { 0x26, "#ASI_TWINX_REAL", }, + { 0x27, "#ASI_TWINX_N", }, + { 0x2A, "#ASI_TWINX_AIUP_L", }, + { 0x2B, "#ASI_TWINX_AIUS_L", }, + { 0x2E, "#ASI_TWINX_REAL_L", }, + { 0x2F, "#ASI_TWINX_NL", }, + { 0xE2, "#ASI_TWINX_P", }, + { 0xE3, "#ASI_TWINX_S", }, + { 0xEA, "#ASI_TWINX_PL", }, + { 0xEB, "#ASI_TWINX_SL", }, { 0, 0 } }; |