diff options
| author | Jan Beulich <jbeulich@suse.com> | 2024-01-19 10:19:15 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-01-19 10:19:15 +0100 |
| commit | 633789901c83d6899685d9011517eb751aa31972 (patch) | |
| tree | f1e8cea2f231f3d45ea075020c80ad64c53e3004 /opcodes | |
| parent | eea4357967b6182459d423c4d919a7cb0219604b (diff) | |
| download | binutils-633789901c83d6899685d9011517eb751aa31972.zip binutils-633789901c83d6899685d9011517eb751aa31972.tar.gz binutils-633789901c83d6899685d9011517eb751aa31972.tar.bz2 | |
x86-64: Dwarf2 register numbers for %bnd<N>
I don't see why we shouldn't record them when they have been allocated,
even if they're (bogusly) named as reserved in the ABI right now.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-reg.tbl | 8 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index f923153..87d2665 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -353,10 +353,10 @@ tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval // Bound registers for MPX -bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval -bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval -bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval -bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval +bnd0, Class=RegBND, 0, 0, Dw2Inval, 126 +bnd1, Class=RegBND, 0, 1, Dw2Inval, 127 +bnd2, Class=RegBND, 0, 2, Dw2Inval, 128 +bnd3, Class=RegBND, 0, 3, Dw2Inval, 129 // No Class=Reg will make these registers rejected for all purposes except // for addressing. This saves creating one extra type for RIP/EIP. rip, Qword, RegRex64, RegIP, Dw2Inval, 16 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 72d5b9f..bdcc3c8 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -44881,19 +44881,19 @@ static const reg_entry i386_regtab[] = { "bnd0", { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 0, { Dw2Inval, Dw2Inval } }, + 0, 0, { Dw2Inval, 126 } }, { "bnd1", { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 1, { Dw2Inval, Dw2Inval } }, + 0, 1, { Dw2Inval, 127 } }, { "bnd2", { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 2, { Dw2Inval, Dw2Inval } }, + 0, 2, { Dw2Inval, 128 } }, { "bnd3", { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, 3, { Dw2Inval, Dw2Inval } }, + 0, 3, { Dw2Inval, 129 } }, { "rip", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }, |