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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:13:24 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:13:24 +0000 |
| commit | 4f51b4bdbbae0b751bb093ebcf568e5808fc87c2 (patch) | |
| tree | 83703bfd05b806e174fab6c53af65045f2a7893c /opcodes | |
| parent | 91ff78946d8fd0c1eb13a65225b72eea3f8b8c17 (diff) | |
| download | binutils-4f51b4bdbbae0b751bb093ebcf568e5808fc87c2.zip binutils-4f51b4bdbbae0b751bb093ebcf568e5808fc87c2.tar.gz binutils-4f51b4bdbbae0b751bb093ebcf568e5808fc87c2.tar.bz2 | |
* gas/config/tc-arm.c (neon_type_mask): Add P64 type.
(type_chk_of_el_type): Handle P64 type.
(el_type_of_type_chk): Likewise.
(do_neon_vmull): Handle VMULL.P64.
* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5f04b9d..c879cb3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,9 @@ 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (neon_opcodes): Handle VMULL.P64. + +2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * arm-dis.c (neon_opcodes): Add support for AES instructions. 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index ef5c752..c0a6479 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -757,6 +757,7 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, /* Three registers of different lengths. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |