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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:20 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:49 +0800 |
| commit | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (patch) | |
| tree | 4a82c5fbaf454ec2fcf147c1134d67b2f38d5879 /opcodes | |
| parent | 7a4ce4a1bcff9710b7dede9797e6d5eb2364c06e (diff) | |
| download | binutils-4a3bc79bf4c0e89c876c930a1e95a02213277460.zip binutils-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.gz binutils-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.bz2 | |
RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/riscv-opc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 599486f..dfd508b 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1931,6 +1931,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadFmv instructions. */ +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, +{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, + /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, {"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, |