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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-15 14:29:31 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | 3521a28f10900ed893f53fcceec2f66c335cb154 (patch) | |
| tree | 2ddacb0f3751437dfdce28490946d167995d3098 /opcodes | |
| parent | f89c290e23c1195bbe6f90980ace3f9a81fde6f1 (diff) | |
| download | binutils-3521a28f10900ed893f53fcceec2f66c335cb154.zip binutils-3521a28f10900ed893f53fcceec2f66c335cb154.tar.gz binutils-3521a28f10900ed893f53fcceec2f66c335cb154.tar.bz2 | |
aarch64: Add support for the SYSP 128-bit system instruction
Mirroring the use of the `sys' - System Instruction assembly
instruction, this implements its 128-bit counterpart, `sysp'.
This optionally takes two contiguous general-purpose registers
starting at an even number or, when these are omitted, by default
sets both of these to xzr.
Syntax:
sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-dis.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 2 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 9 |
3 files changed, 11 insertions, 3 deletions
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 8f99259..7eee365 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -302,7 +302,8 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op aarch64_operand_error *errors ATTRIBUTE_UNUSED) { assert (info->idx == 1 - || info->idx == 3); + || info->idx == 3 + || info->idx == 5); unsigned prev_regno = inst->operands[info->idx - 1].reg.regno; info->reg.regno = (prev_regno == 0x1f) ? 0x1f diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a5f0937..b750904 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1710,7 +1710,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, else if (type == AARCH64_OPND_PAIRREG || type == AARCH64_OPND_PAIRREG_OR_XZR) { - assert (idx == 1 || idx == 3); + assert (idx == 1 || idx == 3 || idx == 5); if (opnds[idx - 1].reg.regno % 2 != 0) { set_syntax_error (mismatch_detail, idx - 1, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b2a8b34..739e78b 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -42,7 +42,7 @@ #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)} #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)} #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)} -#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)} +#define QLF6(a,b,c,d,e,f) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)} /* Qualifiers list. */ @@ -70,6 +70,12 @@ QLF5(X,NIL,CR,CR,NIL), \ } +/* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */ +#define QL_SYSP \ +{ \ + QLF6(NIL,CR,CR,NIL,X,X), \ +} + /* e.g. ADRP <Xd>, <label>. */ #define QL_ADRP \ { \ @@ -4195,6 +4201,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), + D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), |