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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-11-16 14:24:27 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-16 14:24:30 +0000 |
| commit | 281fda33bcf47d5d541e28aac1e5772ebdf1eb1a (patch) | |
| tree | 49b8a44abf44d6bcd32e882e9ef555bc486d64d3 /opcodes | |
| parent | 311276f10c4f85827d3264a2682ae9219917060f (diff) | |
| download | binutils-281fda33bcf47d5d541e28aac1e5772ebdf1eb1a.zip binutils-281fda33bcf47d5d541e28aac1e5772ebdf1eb1a.tar.gz binutils-281fda33bcf47d5d541e28aac1e5772ebdf1eb1a.tar.bz2 | |
aarch64: Add new AT system instructions.
This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/aarch64-opc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e4b3522..4d84071 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] = { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT }, { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT }, { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT }, + { "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT }, + { "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT }, + { "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT }, { 0, CPENS(0,0,0,0), 0 } }; @@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, && AARCH64_CPU_HAS_FEATURE (features, THE)) return true; + if ((reg_value == CPENS (0, C7, C9, 2) + || reg_value == CPENS (4, C7, C9, 2) + || reg_value == CPENS (6, C7, C9, 2)) + && AARCH64_CPU_HAS_FEATURE (features, ATS1A)) + return true; + return false; } |