[ARC] Add arithmetic and logic instructions for nps

This commit completes the implementation of arithmetic and logic
instructions for the NPS-400. These instructions are:

- calcbsd / calcbxd
- calckey / calcxkey
- mxb / imxb
- addl, subl, orl, andl, xorl
- andab / orab
- lbdsize
- bdlen
- csms, csma, cbba
- zncv
- hofs

3 files changed, 293 insertions, 1 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fbde3e1..6b54926 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,28 @@
+2016-06-13  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
+	imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
+	csma, cbba, zncv, and hofs.
+	* arc-opc.c: Add flag classes, insert/extract functions, and operands to
+	support the above instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add andab and orab instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add addl-like instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add mxb and imxb instructions.
+
+2016-06-06  Graham Markall  <graham.markall@embecosm.com>
+
+	* arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
+	instructions.
+
 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
 	* s390-dis.c (option_use_insn_len_bits_p): New file scope
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 473a586..fe6a195 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -191,6 +191,182 @@ DIV_LIKE ("divm", 0x0)
 { "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 { "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 
+{ "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+{ "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+{ "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+{ "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+
+#define ADDL_LIKE(NAME,SUBOP2,SHIM)                                     \
+  { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }},
+
+ADDL_LIKE ("addl", 0xA, NPS_SIMM16)
+ADDL_LIKE ("subl", 0xB, NPS_SIMM16)
+ADDL_LIKE ("orl", 0xC, NPS_UIMM16)
+ADDL_LIKE ("andl", 0xD, NPS_UIMM16)
+ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
+
+{ "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+
+{ "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RC }, { C_F }},
+
+{ "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+
+/* csma a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
+{ "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* csma a,limm,c   0011111000100001F111CCCCCCAAAAAA */
+{ "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* csma a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
+{ "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* csma 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
+{ "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* csma 0,limm,c   0011111000100001F111CCCCCC111110 */
+{ "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* csma 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
+{ "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* csma 0,b,limm   00111bbb00100001FBBB111110111110 */
+{ "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* csma a,b,limm   00111bbb00100001FBBB111110AAAAAA */
+{ "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* csma a,limm,limm    0011111000100001F111111110AAAAAA */
+{ "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* csma a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
+{ "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csma 0,limm,u6   0011111001100001F111uuuuuu111110 */
+{ "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csms a,b,c   00111bbb00101100FBBBCCCCCCAAAAAA */
+{ "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* csma a,limm,c   0011111000101100F111CCCCCCAAAAAA */
+{ "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* csms a,b,u6   00111bbb01101100FBBBuuuuuuAAAAAA */
+{ "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* csms 0,b,c   00111bbb00101100FBBBCCCCCC111110 */
+{ "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* csms 0,limm,c   0011111000101100F111CCCCCC111110 */
+{ "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* csms 0,b,u6   00111bbb01101100FBBBuuuuuu111110 */
+{ "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* csms 0,b,limm   00111bbb00101100FBBB111110111110 */
+{ "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* csms a,b,limm   00111bbb00101100FBBB111110AAAAAA */
+{ "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* csms a,limm,limm   0011111000101100F111111110AAAAAA */
+{ "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* csms a,limm,u6   0011111001101100F111uuuuuuAAAAAA */
+{ "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* csms 0,limm,u6   0011111001101100F111uuuuuu111110 */
+{ "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbba a,b,c   00111bbb00101101FBBBCCCCCCAAAAAA */
+{ "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* cbba a,limm,c    0011111000101101F111CCCCCCAAAAAA */
+{ "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* cbba a,b,u6   00111bbb01101101FBBBuuuuuuAAAAAA */
+{ "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* cbba 0,b,c   00111bbb00101101FBBBCCCCCC111110 */
+{ "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* cbba 0,limm,c   0011111000101101F111CCCCCC111110 */
+{ "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* cbba 0,b,u6   00111bbb01101101FBBBuuuuuu111110 */
+{ "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* cbba 0,b,limm   00111bbb00101101FBBB111110111110 */
+{ "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* cbba a,b,limm   00111bbb00101101FBBB111110AAAAAA */
+{ "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* cbba a,limm,limm   0011111000101101F111111110AAAAAA */
+{ "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* cbba a,limm,u6   0011111001101101F111uuuuuuAAAAAA */
+{ "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* cbba 0,limm,u6   0011111001101101F111uuuuuu111110 */
+{ "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* zncv<.rd|.wr> a,b,c   00111bbb001101010BBBCCCCCCAAAAAA */
+{ "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,b,u6   00111bbb011101010BBBuuuuuuAAAAAA */
+{ "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> b,b,s12   00111bbb101101010BBBssssssSSSSSS */
+{ "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,b,limm   00111bbb001101010BBB111110AAAAAA */
+{ "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,c   00111110001101010111CCCCCCAAAAAA */
+{ "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,u6   00111110011101010111uuuuuuAAAAAA */
+{ "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> a,limm,limm   00111110001101010111111110AAAAAA */
+{ "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,c 00111bbb001101010BBBCCCCCC111110 */
+{ "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,u6   00111bbb011101010BBBuuuuuu111110 */
+{ "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,b,limm   00111bbb001101010BBB111110111110 */
+{ "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,c   00111110001101010111CCCCCC111110 */
+{ "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,u6   00111110011101010111uuuuuu111110 */
+{ "zncv", 0x3e75703e, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+
+/* zncv<.rd|.wr> 0,limm,s12   00111110101101010111ssssssSSSSSS */
+{ "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }},
+
+/* hofs a,b,c */
+{ "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* hofs a,b,min_hofs,psbc */
+{ "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
+
 /****                  Protocol Decoder Instructions                  ****/
 
 /* dctcp b,c  00111bbb001011110bbbcccccc000000 */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 4c69a16..7e0ba46 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1110,6 +1110,55 @@ extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED,
   return value;
 }
 
+#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS)         \
+static unsigned                                                         \
+insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED,                      \
+                   int value ATTRIBUTE_UNUSED,                          \
+                   const char **errmsg ATTRIBUTE_UNUSED)                \
+{                                                                       \
+  if (value < 1 || value > UPPER)                                       \
+    *errmsg = _("Value must be in the range 1 to " #UPPER);             \
+  if (value == UPPER)                                                   \
+    value = 0;                                                          \
+  return insn | (value << SHIFT);                                       \
+}                                                                       \
+                                                                        \
+static int                                                              \
+extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED,                     \
+                    bfd_boolean * invalid ATTRIBUTE_UNUSED)             \
+{                                                                       \
+  int value = (insn >> SHIFT) & ((1 << BITS) - 1);                      \
+  if (value == 0)                                                       \
+    value = UPPER;                                                      \
+  return value;                                                         \
+}
+
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(field_size, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(shift_factor, 9, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bits_to_scramble, 12, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS(bdlen_max_len, 5, 256, 8)
+
+static unsigned
+insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
+                     int value ATTRIBUTE_UNUSED,
+                     const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value < 0 || value > 240)
+    *errmsg = _("Value must be in the range 0 to 240");
+  if ((value % 16) != 0)
+    *errmsg = _("Value must be a multiple of 16");
+  value = value / 16;
+  return insn | (value << 6);
+}
+
+static int
+extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED,
+                      bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 6) & 0xF;
+  return value * 16;
+}
+
 /* Include the generic extract/insert functions.  Order is important
    as some of the functions present in the .h may be disabled via
    defines.  */
@@ -1314,6 +1363,15 @@ const struct arc_flag_operand arc_flag_operands[] =
 
 #define F_NPS_AL     (F_NPS_AR + 1)
   { "al",  1, 1, 0, 1 },
+
+#define F_NPS_S      (F_NPS_AL + 1)
+  { "s",   0, 0, 0, 1 },
+
+#define F_NPS_ZNCV_RD      (F_NPS_S + 1)
+  { "rd",  0, 1, 15, 1 },
+
+#define F_NPS_ZNCV_WR      (F_NPS_ZNCV_RD + 1)
+  { "wr",  1, 1, 15, 1 },
 };
 
 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -1420,6 +1478,12 @@ const struct arc_flag_class arc_flag_classes[] =
 
 #define C_NPS_AR_AL     (C_NPS_SX + 1)
   { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
+
+#define C_NPS_S    (C_NPS_AR_AL + 1)
+  { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
+
+#define C_NPS_ZNCV    (C_NPS_S + 1)
+  { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
 };
 
 const unsigned char flags_none[] = { 0 };
@@ -1785,7 +1849,10 @@ const struct arc_operand arc_operands[] =
 #define NPS_UIMM16		(NPS_BITOP_UIMM8 + 1)
   { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
 
-#define NPS_RFLT_UIMM6		(NPS_UIMM16 + 1)
+#define NPS_SIMM16              (NPS_UIMM16 + 1)
+  { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
+
+#define NPS_RFLT_UIMM6		(NPS_SIMM16 + 1)
   { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
 
 #define NPS_XLDST_UIMM16	(NPS_RFLT_UIMM6 + 1)
@@ -1889,6 +1956,30 @@ const struct arc_operand arc_operands[] =
 
 #define NPS_BITOP_INS_EXT	(NPS_BITOP_MOD1 + 1)
   { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
+
+#define NPS_FIELD_START_POS     (NPS_BITOP_INS_EXT + 1)
+  { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_FIELD_SIZE          (NPS_FIELD_START_POS + 1)
+  { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size },
+
+#define NPS_SHIFT_FACTOR        (NPS_FIELD_SIZE + 1)
+  { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor },
+
+#define NPS_BITS_TO_SCRAMBLE    (NPS_SHIFT_FACTOR + 1)
+  { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
+
+#define NPS_SRC2_POS_5B         (NPS_BITS_TO_SCRAMBLE + 1)
+  { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BDLEN_MAX_LEN       (NPS_SRC2_POS_5B + 1)
+  { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
+
+#define NPS_MIN_HOFS       (NPS_BDLEN_MAX_LEN + 1)
+  { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs },
+
+#define NPS_PSBC       (NPS_MIN_HOFS + 1)
+  { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
 };
 
 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);