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| author | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:11:08 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2019-05-21 18:11:08 +0100 |
| commit | 23d00a419fe67801afc02a87f7ab9c5374b0238e (patch) | |
| tree | cba7cb850ffd1f9e5a741ebbf0c40bb9031c89e8 /opcodes/ChangeLog | |
| parent | cd4797ee054654160fe6c4b6fbecd636b7961e19 (diff) | |
| download | binutils-23d00a419fe67801afc02a87f7ab9c5374b0238e.zip binutils-23d00a419fe67801afc02a87f7ab9c5374b0238e.tar.gz binutils-23d00a419fe67801afc02a87f7ab9c5374b0238e.tar.bz2 | |
[binutils, Arm] Add support for shift instructions in MVE
This patch adds the following instructions which are part of
Armv8.1-M MVE:
ASRL (imm)
ASRL (reg)
LSLL (imm)
LSLL (reg)
LSRL
SQRSHRL
SRQSHR
SQSHLL
SQSHL
SRSHRL
SRSHR
UQRSHLL
UQRSHL
UQSHLL
UQSHL
URSHLL
URSHL
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): New entries for
OP_RRnpcsp_I32 (register or integer operands).
(do_mve_scalar_shift): New.
(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
* testsuite/gas/arm/mve-shift.d: New.
* testsuite/gas/arm/mve-shift.s: New.
* testsuite/gas/arm/mve-shift-bad.d: New.
* testsuite/gas/arm/mve-shift-bad.s: New.
* testsuite/gas/arm/mve-shift-bad.l: New.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (emun mve_instructions): Updated for new instructions.
(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
uqshl, urshrl and urshr.
(is_mve_okay_in_it): Add new instructions to TRUE list.
(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
(print_insn_mve): Updated to accept new %j,
%<bitfield>m and %<bitfield>n patterns.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7f061c2..e6950ac 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2019-05-21 Sudakshina Das <sudi.das@arm.com> + + * arm-dis.c (emun mve_instructions): Updated for new instructions. + (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, + sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, + uqshl, urshrl and urshr. + (is_mve_okay_in_it): Add new instructions to TRUE list. + (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. + (print_insn_mve): Updated to accept new %j, + %<bitfield>m and %<bitfield>n patterns. + 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com> * mips-opc.c (mips_builtin_opcodes): Change source register |