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| author | Matthieu Longo <matthieu.longo@arm.com> | 2025-07-21 10:53:13 +0100 |
|---|---|---|
| committer | saurabhjha <saurabhjha@sourceware.org> | 2025-10-06 17:56:26 +0000 |
| commit | 84835d6288e070f401ff1d6a5d13da1d74b5243a (patch) | |
| tree | b1875708edf722d74868294a14df616a73c41f49 /gdb/python/py-function.c | |
| parent | e4b118633a2e64e144a5f6a03888f8f4e9fa0994 (diff) | |
| download | binutils-84835d6288e070f401ff1d6a5d13da1d74b5243a.zip binutils-84835d6288e070f401ff1d6a5d13da1d74b5243a.tar.gz binutils-84835d6288e070f401ff1d6a5d13da1d74b5243a.tar.bz2 | |
aarch64: GICv5 PPI system registers
This patch adds support for PPI registers on AArch64, available via the
Generic Interrupt Controller v5 feature, and enabled via the +gcie flag.
- icc_ppi_cactiver[0,1]_el1
- icc_ppi_cpendr[0,1]_el1
- icc_ppi_enabler[0,1]_el1
- icc_ppi_hmr[0,1]_el1 (RO)
- icc_ppi_priorityr[0,15]_el1
- icc_ppi_sactiver[0,1]_el1
- icc_ppi_spendr[0,1]_el1
Also, the new system register 'icc_ppi_priorityr8_el1' clashed with the
encoding of 's3_0_c12_c15_0' used in a test for the generic syntax of
system registers using mrs and msr.
This patch replaces 's3_0_c12_c15_0' in the test by an unused encoding:
s3_7_c0_c15_0.
Diffstat (limited to 'gdb/python/py-function.c')
0 files changed, 0 insertions, 0 deletions