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| author | Matthieu Longo <matthieu.longo@arm.com> | 2025-07-18 16:47:44 +0100 |
|---|---|---|
| committer | saurabhjha <saurabhjha@sourceware.org> | 2025-10-06 17:56:26 +0000 |
| commit | e4b118633a2e64e144a5f6a03888f8f4e9fa0994 (patch) | |
| tree | 63a547d9363d66e7a48cc486d78e861d303654a2 /gdb/python/py-function.c | |
| parent | a149def232c6a143651a5943dcdb1aa8aa2f653b (diff) | |
| download | binutils-e4b118633a2e64e144a5f6a03888f8f4e9fa0994.zip binutils-e4b118633a2e64e144a5f6a03888f8f4e9fa0994.tar.gz binutils-e4b118633a2e64e144a5f6a03888f8f4e9fa0994.tar.bz2 | |
aarch64: GICv5 CPU interface system registers
This patch adds support for 13 new AArch64 system registers for the CPU
interface, which are enabled on using Generic Interrupt Controller v5
(+gcie flag) feature:
- 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3
ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3.
- 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1,
ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1.
Note: the already-existing ID_AA64PFR2_EL1 register is required by the
GICv5 feature.
Diffstat (limited to 'gdb/python/py-function.c')
0 files changed, 0 insertions, 0 deletions