Use bool in gas

	* as.h (POISON_BFD_BOOLEAN): Define.
	* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
	* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
	* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
	* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
	* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
	* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
	* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
	* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
	* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
	* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
	* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
	* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
	* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
	* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
	* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
	* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
	* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
	* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
	* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
	* config/tc-metag.c, * config/tc-metag.h,
	* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
	* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
	* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
	* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
	* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
	* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
	* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
	* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
	* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
	* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
	* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
	* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
	* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
	* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
	* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
	* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
	* config/tc-xstormy16.c, * config/tc-xstormy16.h,
	* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
	* config/tc-z8k.c, * config/xtensa-istack.h,
	* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
	* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
	* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
	* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
	with bool, FALSE with false, and TRUE with true.

1 files changed, 114 insertions, 114 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 429732f..2bce5e8 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -176,7 +176,7 @@ static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
 static unsigned xlen = 0; /* The width of an x-register.  */
 static unsigned abi_xlen = 0; /* The width of a pointer in the ABI.  */
-static bfd_boolean rve_abi = FALSE;
+static bool rve_abi = false;
 enum float_abi
 {
   FLOAT_ABI_DEFAULT = -1,
@@ -280,7 +280,7 @@ static struct riscv_set_options riscv_opts =
 };
 
 static void
-riscv_set_rvc (bfd_boolean rvc_value)
+riscv_set_rvc (bool rvc_value)
 {
   if (rvc_value)
     elf_flags |= EF_RISCV_RVC;
@@ -289,25 +289,25 @@ riscv_set_rvc (bfd_boolean rvc_value)
 }
 
 static void
-riscv_set_rve (bfd_boolean rve_value)
+riscv_set_rve (bool rve_value)
 {
   riscv_opts.rve = rve_value;
 }
 
 static riscv_subset_list_t riscv_subsets;
 
-static bfd_boolean
+static bool
 riscv_subset_supports (const char *feature)
 {
   struct riscv_subset_t *subset;
 
   if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
-    return TRUE;
+    return true;
 
   return riscv_lookup_subset (&riscv_subsets, feature, &subset);
 }
 
-static bfd_boolean
+static bool
 riscv_multi_subset_supports (enum riscv_insn_class insn_class)
 {
   switch (insn_class)
@@ -345,7 +345,7 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
 
     default:
       as_fatal ("internal: unreachable");
-      return FALSE;
+      return false;
     }
 }
 
@@ -419,10 +419,10 @@ riscv_set_arch (const char *s)
 }
 
 /* Indicate -mabi option is explictly set.  */
-static bfd_boolean explicit_mabi = FALSE;
+static bool explicit_mabi = false;
 
 static void
-riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve)
+riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
 {
   abi_xlen = new_xlen;
   float_abi = new_float_abi;
@@ -438,11 +438,11 @@ riscv_set_abi_by_arch (void)
   if (!explicit_mabi)
     {
       if (riscv_subset_supports ("q"))
-	riscv_set_abi (xlen, FLOAT_ABI_QUAD, FALSE);
+	riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
       else if (riscv_subset_supports ("d"))
-	riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, FALSE);
+	riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
       else
-	riscv_set_abi (xlen, FLOAT_ABI_SOFT, FALSE);
+	riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
     }
   else
     {
@@ -493,13 +493,13 @@ const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "rRsSfFdDxXpP";
 
 /* Indicate we are already assemble any instructions or not.  */
-static bfd_boolean start_assemble = FALSE;
+static bool start_assemble = false;
 
 /* Indicate ELF attributes are explicitly set.  */
-static bfd_boolean explicit_attr = FALSE;
+static bool explicit_attr = false;
 
 /* Indicate CSR or priv instructions are explicitly used.  */
-static bfd_boolean explicit_priv_attr = FALSE;
+static bool explicit_priv_attr = false;
 
 /* Macros for encoding relaxation state for RVC branches and far jumps.  */
 #define RELAX_BRANCH_ENCODE(uncond, rvc, length)	\
@@ -795,7 +795,7 @@ riscv_init_csr_hash (const char *name,
 		     enum riscv_spec_class abort_version)
 {
   struct riscv_csr_extra *entry, *pre_entry;
-  bfd_boolean need_enrty = TRUE;
+  bool need_enrty = true;
 
   pre_entry = NULL;
   entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
@@ -805,7 +805,7 @@ riscv_init_csr_hash (const char *name,
 	  && entry->address == address
 	  && entry->define_version == define_version
 	  && entry->abort_version == abort_version)
-	need_enrty = FALSE;
+	need_enrty = false;
       pre_entry = entry;
       entry = entry->next;
     }
@@ -843,8 +843,8 @@ riscv_csr_address (const char *csr_name,
 {
   struct riscv_csr_extra *saved_entry = entry;
   enum riscv_csr_class csr_class = entry->csr_class;
-  bfd_boolean need_check_version = TRUE;
-  bfd_boolean result = TRUE;
+  bool need_check_version = true;
+  bool result = true;
 
   switch (csr_class)
     {
@@ -856,10 +856,10 @@ riscv_csr_address (const char *csr_name,
       break;
     case CSR_CLASS_F:
       result = riscv_subset_supports ("f");
-      need_check_version = FALSE;
+      need_check_version = false;
       break;
     case CSR_CLASS_DEBUG:
-      need_check_version = FALSE;
+      need_check_version = false;
       break;
     default:
       as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
@@ -927,7 +927,7 @@ reg_lookup_internal (const char *s, enum reg_class class)
   return DECODE_REG_NUM (r);
 }
 
-static bfd_boolean
+static bool
 reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
 {
   char *e;
@@ -955,31 +955,31 @@ reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
   return reg >= 0;
 }
 
-static bfd_boolean
+static bool
 arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
 {
   const char *p = strchr (*s, ',');
   size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
 
   if (len == 0)
-    return FALSE;
+    return false;
 
   for (i = 0; i < size; i++)
     if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
       {
 	*regnop = i;
 	*s += len;
-	return TRUE;
+	return true;
       }
 
-  return FALSE;
+  return false;
 }
 
 /* For consistency checking, verify that all bits are specified either
    by the match/mask part of the instruction definition, or by the
    operand list. The `length` could be 0, 4 or 8, 0 for auto detection.  */
 
-static bfd_boolean
+static bool
 validate_riscv_insn (const struct riscv_opcode *opc, int length)
 {
   const char *p = opc->args;
@@ -999,7 +999,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
     {
       as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
 	      opc->name, opc->args);
-      return FALSE;
+      return false;
     }
 
 #define USE_BITS(mask,shift)	(used_bits |= ((insn_t)(mask) << (shift)))
@@ -1050,14 +1050,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		  as_bad (_("internal: bad RISC-V opcode "
 			    "(unknown operand type `CF%c'): %s %s"),
 			  c, opc->name, opc->args);
-		  return FALSE;
+		  return false;
 	      }
 	    break;
 	  default:
 	    as_bad (_("internal: bad RISC-V opcode "
 		      "(unknown operand type `C%c'): %s %s"),
 		    c, opc->name, opc->args);
-	    return FALSE;
+	    return false;
 	  }
 	break;
       case ',': break;
@@ -1105,7 +1105,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      as_bad (_("internal: bad RISC-V opcode "
 			"(unknown operand type `F%c'): %s %s"),
 		      c, opc->name, opc->args);
-	    return FALSE;
+	    return false;
 	  }
 	break;
       case 'O': /* Opcode for .insn directive.  */
@@ -1117,14 +1117,14 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	      as_bad (_("internal: bad RISC-V opcode "
 			"(unknown operand type `F%c'): %s %s"),
 		      c, opc->name, opc->args);
-	     return FALSE;
+	     return false;
 	  }
 	break;
       default:
 	as_bad (_("internal: bad RISC-V opcode "
 		  "(unknown operand type `%c'): %s %s"),
 		c, opc->name, opc->args);
-	return FALSE;
+	return false;
       }
 #undef USE_BITS
   if (used_bits != required_bits)
@@ -1133,9 +1133,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		"(bits 0x%lx undefined): %s %s"),
 	      ~(unsigned long)(used_bits & required_bits),
 	      opc->name, opc->args);
-      return FALSE;
+      return false;
     }
-  return TRUE;
+  return true;
 }
 
 struct percent_op_match
@@ -1149,7 +1149,7 @@ struct percent_op_match
 
 static htab_t
 init_opcode_hash (const struct riscv_opcode *opcodes,
-		  bfd_boolean insn_directive_p)
+		  bool insn_directive_p)
 {
   int i = 0;
   int length;
@@ -1193,8 +1193,8 @@ md_begin (void)
   if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
     as_warn (_("could not set architecture and machine"));
 
-  op_hash = init_opcode_hash (riscv_opcodes, FALSE);
-  insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
+  op_hash = init_opcode_hash (riscv_opcodes, false);
+  insn_type_hash = init_opcode_hash (riscv_insn_types, true);
 
   reg_names_hash = str_htab_create ();
   hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
@@ -1285,7 +1285,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
 
 	  ip->fixp = fix_new_exp (ip->frag, ip->where,
 				  bfd_get_reloc_size (howto),
-				  address_expr, FALSE, reloc_type);
+				  address_expr, false, reloc_type);
 
 	  ip->fixp->fx_tcbit = riscv_opts.relax;
 	}
@@ -1414,7 +1414,7 @@ normalize_constant_expr (expressionS *ex)
 
 static void
 check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
-		     bfd_boolean maybe_csr)
+		     bool maybe_csr)
 {
   if (ex->X_op == O_big)
     as_bad (_("unsupported large constant"));
@@ -1536,7 +1536,7 @@ load_const (int reg, expressionS *ep)
 /* Zero extend and sign extend byte/half-word/word.  */
 
 static void
-riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
+riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
 {
   if (sign)
     {
@@ -1673,19 +1673,19 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
       break;
 
     case M_ZEXTH:
-      riscv_ext (rd, rs1, xlen - 16, FALSE);
+      riscv_ext (rd, rs1, xlen - 16, false);
       break;
 
     case M_ZEXTW:
-      riscv_ext (rd, rs1, xlen - 32, FALSE);
+      riscv_ext (rd, rs1, xlen - 32, false);
       break;
 
     case M_SEXTB:
-      riscv_ext (rd, rs1, xlen - 8, TRUE);
+      riscv_ext (rd, rs1, xlen - 8, true);
       break;
 
     case M_SEXTH:
-      riscv_ext (rd, rs1, xlen - 16, TRUE);
+      riscv_ext (rd, rs1, xlen - 16, true);
       break;
 
     default:
@@ -1736,7 +1736,7 @@ static const struct percent_op_match percent_op_null[] =
    move *STR over the operator and store its relocation code in *RELOC.
    Leave both *STR and *RELOC alone when returning false.  */
 
-static bfd_boolean
+static bool
 parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
 		  const struct percent_op_match *percent_op)
 {
@@ -1760,9 +1760,9 @@ parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
 		    "current ABI", percent_op->str);
 	    *reloc = BFD_RELOC_UNUSED;
 	  }
-	return TRUE;
+	return true;
       }
-  return FALSE;
+  return false;
 }
 
 static void
@@ -1863,7 +1863,7 @@ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
    "lw t0, (t1)" is shorthand for "lw t0, 0(t1)".  Return TRUE iff such
    an implicit offset was detected.  */
 
-static bfd_boolean
+static bool
 riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
 {
   /* Check whether there is only a single bracketed expression left.
@@ -1872,10 +1872,10 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
     {
       ep->X_op = O_constant;
       ep->X_add_number = 0;
-      return TRUE;
+      return true;
     }
 
-  return FALSE;
+  return false;
 }
 
 /* All RISC-V CSR instructions belong to one of these classes.  */
@@ -1909,7 +1909,7 @@ riscv_csr_insn_type (insn_t insn)
    CSR when RS1 isn't zero.  The CSR is read only if the [11:10] bits of
    CSR address is 0x3.  */
 
-static bfd_boolean
+static bool
 riscv_csr_read_only_check (insn_t insn)
 {
   int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
@@ -1922,9 +1922,9 @@ riscv_csr_read_only_check (insn_t insn)
 	    || csr_insn == INSN_CSRRC)
 	   && rs1 != 0)
 	  || csr_insn == INSN_CSRRW))
-    return FALSE;
+    return false;
 
-  return TRUE;
+  return true;
 }
 
 /* Return True if it is a privileged instruction.  Otherwise, return FALSE.
@@ -1940,7 +1940,7 @@ riscv_csr_read_only_check (insn_t insn)
    dret is defined in the debug spec, so it should be checked in the future,
    too.  */
 
-static bfd_boolean
+static bool
 riscv_is_priv_insn (insn_t insn)
 {
   return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
@@ -1971,7 +1971,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
   const struct percent_op_match *p;
   const char *error = "unrecognized opcode";
   /* Indicate we are assembling instruction with CSR.  */
-  bfd_boolean insn_with_csr = FALSE;
+  bool insn_with_csr = false;
 
   /* Parse the name of the instruction.  Terminate the string if whitespace
      is found so that str_hash_find only sees the name part of the string.  */
@@ -2020,7 +2020,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		    break;
 
 		  if (riscv_is_priv_insn (ip->insn_opcode))
-		    explicit_priv_attr = TRUE;
+		    explicit_priv_attr = true;
 
 		  /* Check if we write a read-only CSR by the CSR
 		     instruction.  */
@@ -2033,14 +2033,14 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      if (save_c)
 			*(argsStart - 1) = save_c;
 		      as_warn (_("read-only CSR is written `%s'"), str);
-		      insn_with_csr = FALSE;
+		      insn_with_csr = false;
 		    }
 		}
 	      if (*s != '\0')
 		break;
 	      /* Successful assembly.  */
 	      error = NULL;
-	      insn_with_csr = FALSE;
+	      insn_with_csr = false;
 	      goto out;
 
 	    case 'C': /* RVC */
@@ -2355,7 +2355,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 
 	    case '<': /* Shift amount, 0 - 31.  */
 	      my_getExpression (imm_expr, s);
-	      check_absolute_expr (ip, imm_expr, FALSE);
+	      check_absolute_expr (ip, imm_expr, false);
 	      if ((unsigned long) imm_expr->X_add_number > 31)
 		as_bad (_("improper shift amount (%lu)"),
 			(unsigned long) imm_expr->X_add_number);
@@ -2366,7 +2366,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 
 	    case '>': /* Shift amount, 0 - (XLEN-1).  */
 	      my_getExpression (imm_expr, s);
-	      check_absolute_expr (ip, imm_expr, FALSE);
+	      check_absolute_expr (ip, imm_expr, false);
 	      if ((unsigned long) imm_expr->X_add_number >= xlen)
 		as_bad (_("improper shift amount (%lu)"),
 			(unsigned long) imm_expr->X_add_number);
@@ -2377,7 +2377,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 
 	    case 'Z': /* CSRRxI immediate.  */
 	      my_getExpression (imm_expr, s);
-	      check_absolute_expr (ip, imm_expr, FALSE);
+	      check_absolute_expr (ip, imm_expr, false);
 	      if ((unsigned long) imm_expr->X_add_number > 31)
 		as_bad (_("improper CSRxI immediate (%lu)"),
 			(unsigned long) imm_expr->X_add_number);
@@ -2387,14 +2387,14 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      continue;
 
 	    case 'E': /* Control register.  */
-	      insn_with_csr = TRUE;
-	      explicit_priv_attr = TRUE;
+	      insn_with_csr = true;
+	      explicit_priv_attr = true;
 	      if (reg_lookup (&s, RCLASS_CSR, &regno))
 		INSERT_OPERAND (CSR, *ip, regno);
 	      else
 		{
 		  my_getExpression (imm_expr, s);
-		  check_absolute_expr (ip, imm_expr, TRUE);
+		  check_absolute_expr (ip, imm_expr, true);
 		  if ((unsigned long) imm_expr->X_add_number > 0xfff)
 		    as_bad (_("improper CSR address (%lu)"),
 			    (unsigned long) imm_expr->X_add_number);
@@ -2712,7 +2712,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	}
       s = argsStart;
       error = _("illegal operands");
-      insn_with_csr = FALSE;
+      insn_with_csr = false;
     }
 
  out:
@@ -2734,7 +2734,7 @@ md_assemble (char *str)
      before assembling.  */
   if (!start_assemble)
     {
-      start_assemble = TRUE;
+      start_assemble = true;
 
       riscv_set_abi_by_arch ();
       if (!riscv_set_default_priv_spec (NULL))
@@ -2823,59 +2823,59 @@ md_parse_option (int c, const char *arg)
       break;
 
     case OPTION_NO_PIC:
-      riscv_opts.pic = FALSE;
+      riscv_opts.pic = false;
       break;
 
     case OPTION_PIC:
-      riscv_opts.pic = TRUE;
+      riscv_opts.pic = true;
       break;
 
     case OPTION_MABI:
       if (strcmp (arg, "ilp32") == 0)
-	riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE);
+	riscv_set_abi (32, FLOAT_ABI_SOFT, false);
       else if (strcmp (arg, "ilp32e") == 0)
-	riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE);
+	riscv_set_abi (32, FLOAT_ABI_SOFT, true);
       else if (strcmp (arg, "ilp32f") == 0)
-	riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE);
+	riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
       else if (strcmp (arg, "ilp32d") == 0)
-	riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE);
+	riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
       else if (strcmp (arg, "ilp32q") == 0)
-	riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE);
+	riscv_set_abi (32, FLOAT_ABI_QUAD, false);
       else if (strcmp (arg, "lp64") == 0)
-	riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE);
+	riscv_set_abi (64, FLOAT_ABI_SOFT, false);
       else if (strcmp (arg, "lp64f") == 0)
-	riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE);
+	riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
       else if (strcmp (arg, "lp64d") == 0)
-	riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE);
+	riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
       else if (strcmp (arg, "lp64q") == 0)
-	riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE);
+	riscv_set_abi (64, FLOAT_ABI_QUAD, false);
       else
 	return 0;
-      explicit_mabi = TRUE;
+      explicit_mabi = true;
       break;
 
     case OPTION_RELAX:
-      riscv_opts.relax = TRUE;
+      riscv_opts.relax = true;
       break;
 
     case OPTION_NO_RELAX:
-      riscv_opts.relax = FALSE;
+      riscv_opts.relax = false;
       break;
 
     case OPTION_ARCH_ATTR:
-      riscv_opts.arch_attr = TRUE;
+      riscv_opts.arch_attr = true;
       break;
 
     case OPTION_NO_ARCH_ATTR:
-      riscv_opts.arch_attr = FALSE;
+      riscv_opts.arch_attr = false;
       break;
 
     case OPTION_CSR_CHECK:
-      riscv_opts.csr_check = TRUE;
+      riscv_opts.csr_check = true;
       break;
 
     case OPTION_NO_CSR_CHECK:
-      riscv_opts.csr_check = FALSE;
+      riscv_opts.csr_check = false;
       break;
 
     case OPTION_MISA_SPEC:
@@ -2928,14 +2928,14 @@ riscv_after_parse_args (void)
   riscv_set_arch (default_arch_with_ext);
 
   /* Add the RVC extension, regardless of -march, to support .option rvc.  */
-  riscv_set_rvc (FALSE);
+  riscv_set_rvc (false);
   if (riscv_subset_supports ("c"))
-    riscv_set_rvc (TRUE);
+    riscv_set_rvc (true);
 
   /* Enable RVE if specified by the -march option.  */
-  riscv_set_rve (FALSE);
+  riscv_set_rve (false);
   if (riscv_subset_supports ("e"))
-    riscv_set_rve (TRUE);
+    riscv_set_rve (true);
 
   /* If the CIE to be produced has not been overridden on the command line,
      then produce version 3 by default.  This allows us to use the full
@@ -2957,7 +2957,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   unsigned int subtype;
   bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
-  bfd_boolean relaxable = FALSE;
+  bool relaxable = false;
   offsetT loc;
   segT sub_segment;
 
@@ -2972,8 +2972,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
 		  | bfd_getl32 (buf), buf);
       if (fixP->fx_addsy == NULL)
-	fixP->fx_done = TRUE;
-      relaxable = TRUE;
+	fixP->fx_done = true;
+      relaxable = true;
       break;
 
     case BFD_RELOC_RISCV_GOT_HI20:
@@ -2993,7 +2993,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_RISCV_TPREL_LO12_I:
     case BFD_RELOC_RISCV_TPREL_LO12_S:
     case BFD_RELOC_RISCV_TPREL_ADD:
-      relaxable = TRUE;
+      relaxable = true;
       /* Fall through.  */
 
     case BFD_RELOC_RISCV_TLS_GOT_HI20:
@@ -3166,7 +3166,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
     case BFD_RELOC_RISCV_CALL:
     case BFD_RELOC_RISCV_CALL_PLT:
-      relaxable = TRUE;
+      relaxable = true;
       break;
 
     case BFD_RELOC_RISCV_PCREL_HI20:
@@ -3265,21 +3265,21 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
   *input_line_pointer = '\0';
 
   if (strcmp (name, "rvc") == 0)
-    riscv_set_rvc (TRUE);
+    riscv_set_rvc (true);
   else if (strcmp (name, "norvc") == 0)
-    riscv_set_rvc (FALSE);
+    riscv_set_rvc (false);
   else if (strcmp (name, "pic") == 0)
-    riscv_opts.pic = TRUE;
+    riscv_opts.pic = true;
   else if (strcmp (name, "nopic") == 0)
-    riscv_opts.pic = FALSE;
+    riscv_opts.pic = false;
   else if (strcmp (name, "relax") == 0)
-    riscv_opts.relax = TRUE;
+    riscv_opts.relax = true;
   else if (strcmp (name, "norelax") == 0)
-    riscv_opts.relax = FALSE;
+    riscv_opts.relax = false;
   else if (strcmp (name, "csr-check") == 0)
-    riscv_opts.csr_check = TRUE;
+    riscv_opts.csr_check = true;
   else if (strcmp (name, "no-csr-check") == 0)
-    riscv_opts.csr_check = FALSE;
+    riscv_opts.csr_check = false;
   else if (strcmp (name, "push") == 0)
     {
       struct riscv_option_stack *s;
@@ -3333,7 +3333,7 @@ s_dtprel (int bytes)
 
   p = frag_more (bytes);
   md_number_to_chars (p, 0, bytes);
-  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
 	       (bytes == 8
 		? BFD_RELOC_RISCV_TLS_DTPREL64
 		: BFD_RELOC_RISCV_TLS_DTPREL32));
@@ -3378,7 +3378,7 @@ riscv_make_nops (char *buf, bfd_vma bytes)
    will later relax to the correct number of NOPs.  We can't compute
    the correct alignment now because of other linker relaxations.  */
 
-bfd_boolean
+bool
 riscv_frag_align_code (int n)
 {
   bfd_vma bytes = (bfd_vma) 1 << n;
@@ -3390,11 +3390,11 @@ riscv_frag_align_code (int n)
   /* If we are moving to a smaller alignment than the instruction size, then no
      alignment is required. */
   if (bytes <= insn_alignment)
-    return TRUE;
+    return true;
 
   /* When not relaxing, riscv_handle_align handles code alignment.  */
   if (!riscv_opts.relax)
-    return FALSE;
+    return false;
 
   nops = frag_more (worst_case_bytes);
 
@@ -3404,9 +3404,9 @@ riscv_frag_align_code (int n)
   riscv_make_nops (nops, worst_case_bytes);
 
   fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
-	       &ex, FALSE, BFD_RELOC_RISCV_ALIGN);
+	       &ex, false, BFD_RELOC_RISCV_ALIGN);
 
-  return TRUE;
+  return true;
 }
 
 /* Implement HANDLE_ALIGN.  */
@@ -3452,7 +3452,7 @@ riscv_handle_align (fragS *fragP)
 int
 md_estimate_size_before_relax (fragS *fragp, asection *segtype)
 {
-  return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE));
+  return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
 }
 
 /* Translate internal representation of relocation info to BFD target
@@ -3494,7 +3494,7 @@ riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
   if (RELAX_BRANCH_P (fragp->fr_subtype))
     {
       offsetT old_var = fragp->fr_var;
-      fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
+      fragp->fr_var = relaxed_branch_length (fragp, sec, true);
       return fragp->fr_var - old_var;
     }
 
@@ -3556,7 +3556,7 @@ md_convert_frag_branch (fragS *fragp)
 	    reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
 		    ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
 	    fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				2, &exp, FALSE, reloc);
+				2, &exp, false, reloc);
 	    buf += 2;
 	    goto done;
 
@@ -3580,7 +3580,7 @@ md_convert_frag_branch (fragS *fragp)
     jump:
       /* Jump to the target.  */
       fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-			  4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
+			  4, &exp, false, BFD_RELOC_RISCV_JMP);
       bfd_putl32 (MATCH_JAL, buf);
       buf += 4;
       break;
@@ -3589,7 +3589,7 @@ md_convert_frag_branch (fragS *fragp)
       reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
 	      ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
       fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-			  4, &exp, FALSE, reloc);
+			  4, &exp, false, reloc);
       buf += 4;
       break;
 
@@ -3840,7 +3840,7 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
   unsigned old_xlen;
   obj_attribute *attr;
 
-  explicit_attr = TRUE;
+  explicit_attr = true;
   switch (tag)
     {
     case Tag_RISCV_arch: