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path: root/p/riscv_test.h
AgeCommit message (Expand)AuthorFilesLines
2016-03-02WIP on priv spec v1.9Andrew Waterman1-5/+4
2016-02-28WIP on priv spec v1.9Andrew Waterman1-39/+34
2015-09-28make sure TESTNUM is initializedHoward Mao1-0/+1
2015-09-20Remove Hwacha v3 supportAndrew Waterman1-27/+0
2015-07-17don't pass fpu/vector tests when fpu/vector not presentYunsup Lee1-10/+1
2015-06-23Avoid "csrw stvec" if stvec_handler doesn't exist.Christopher Celio1-1/+2
2015-05-19Improve coverage of VM testsAndrew Waterman1-2/+0
2015-05-11Initialize FCSRAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-32/+13
2015-04-03Don't assume initial values of mstatus.ua/saAndrew Waterman1-5/+15
2015-03-30Don't rely on mstatus.fs to test FPU presenceAndrew Waterman1-9/+11
2015-03-25add mtvec_handler to machine traps from user landYunsup Lee1-11/+22
2015-03-24Don't assume PRV1/2 and IE1/2 are resetAndrew Waterman1-2/+4
2015-03-17relay hwacha cause/aux to scause/sbadaddrYunsup Lee1-1/+11
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman1-7/+7
2015-03-16clean up pt and vector environmentsYunsup Lee1-3/+17
2015-03-12Use hcall instead of mcallAndrew Waterman1-6/+6
2015-03-12Update to new privileged specAndrew Waterman1-14/+76
2015-01-09Add LICENSEAndrew Waterman1-0/+2
2015-01-04Avoid deprecated "b" pseudo-op; use "j" insteadAndrew Waterman1-2/+2
2014-03-03need to modify status register *before* enabling interruptsYunsup Lee1-2/+2
2014-02-25make physical timer env work againYunsup Lee1-0/+2
2014-01-31Support RV32S testsAndrew Waterman1-0/+5
2014-01-31Use TESTNUM instead of x28 directlyAndrew Waterman1-7/+5
2014-01-16Source test failure value from correct registerAndrew Waterman1-4/+4
2013-11-24Update to new privileged modeAndrew Waterman1-17/+20
2013-11-13split out envs from riscv-testsYunsup Lee1-0/+117
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