rocket-tools/riscv-tests/env.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
master	Support setting V-env LFSR bits with a compiler flag (#43)	Jerry Zhao	10 months
priv-1.10	Fix physical load address for recent binutils	Andrew Waterman	7 years
priv-1.9	Support RV32 virtual memory tests	Andrew Waterman	8 years
riscv-test-env-sail	created a branch for the sail-riscv testing env	William McSpaddden	4 weeks
vectorless	disable vector trap handling	Howard Mao	9 years


Age	Commit message	Author	Files	Lines
2016-03-14	Support RV32 virtual memory testspriv-1.9	Andrew Waterman	4	-13/+129
2016-03-02	WIP on priv spec v1.9	Andrew Waterman	2	-7/+43
2016-02-28	WIP on priv spec v1.9	Andrew Waterman	6	-178/+147
2015-11-06	Add custom opcodes back to encoding.h	Andrew Waterman	1	-76/+172
2015-09-28	make sure TESTNUM is initialized	Howard Mao	1	-0/+1
2015-09-20	Remove Hwacha v3 support	Andrew Waterman	7	-878/+533
2015-07-17	don't pass fpu/vector tests when fpu/vector not present	Yunsup Lee	1	-10/+1
2015-07-06	Coherence torture test for VM tests	Andrew Waterman	1	-1/+24
2015-07-05	New M-mode timers; don't use sscratch in M-mode	Andrew Waterman	2	-50/+78
2015-06-23	Avoid "csrw stvec" if stvec_handler doesn't exist.	Christopher Celio	1	-1/+2
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