diff options
Diffstat (limited to 'p/riscv_test.h')
| -rw-r--r-- | p/riscv_test.h | 45 |
1 files changed, 13 insertions, 32 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index a94c81c..a3cb7c2 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -27,18 +27,15 @@ #define RVTEST_RV32U \ .macro init; \ - RVTEST_32_ENABLE; \ .endm #define RVTEST_RV32UF \ .macro init; \ - RVTEST_32_ENABLE; \ RVTEST_FP_ENABLE; \ .endm #define RVTEST_RV32UV \ .macro init; \ - RVTEST_32_ENABLE; \ RVTEST_FP_ENABLE; \ RVTEST_VEC_ENABLE; \ .endm @@ -62,32 +59,19 @@ #define RVTEST_RV32M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ - RVTEST_32_ENABLE; \ .endm #define RVTEST_RV32S \ .macro init; \ RVTEST_ENABLE_SUPERVISOR; \ - RVTEST_32_ENABLE; \ .endm -#define RVTEST_32_ENABLE \ - li a0, (MSTATUS64_UA | MSTATUS64_SA) >> 31; \ - slli a0, a0, 31; \ - csrc mstatus, a0 - #ifdef __riscv64 -# define RVTEST_64_ENABLE \ - RVTEST_32_ENABLE; \ - li a0, UA_RV64 * (MSTATUS64_UA & ~(MSTATUS64_UA<<1)); \ - csrs mstatus, a0; \ - li a0, UA_RV64 * (MSTATUS64_SA & ~(MSTATUS64_SA<<1)); \ - csrs mstatus, a0 +# define CHECK_XLEN csrr a0, mcpuid; bltz a0, 1f; RVTEST_PASS; 1: #else -# define RVTEST_64_ENABLE +# define CHECK_XLEN csrr a0, mcpuid; bgez a0, 1f; RVTEST_PASS; 1: #endif - #define RVTEST_ENABLE_SUPERVISOR \ li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1); \ csrs mstatus, a0; \ @@ -97,10 +81,13 @@ csrs mstatus, a0; \ #define RVTEST_FP_ENABLE \ - li a0, SSTATUS_FS & (SSTATUS_FS >> 1); \ - csrs sstatus, a0; \ -test_fpu_presence: \ - fssr x0; \ + li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ + csrs mstatus, a0; \ + csrr a0, mcpuid; \ + andi a0, a0, 1 << ('D' - 'A'); /* test for D extension */ \ + bnez a0, 1f; \ + RVTEST_PASS; /* "pass" the test if FPU not present */ \ +1: #define RVTEST_VEC_ENABLE \ li a0, SSTATUS_XS & (SSTATUS_XS >> 1); \ @@ -112,7 +99,7 @@ test_fpu_presence: \ 2: \ #define RISCV_MULTICORE_DISABLE \ - csrr a0, hartid; \ + csrr a0, mhartid; \ 1: bnez a0, 1b #define EXTRA_TVEC_USER @@ -127,7 +114,6 @@ test_fpu_presence: \ .align 6; \ .weak stvec_handler; \ .weak mtvec_handler; \ - .weak test_fpu_presence; \ tvec_user: \ EXTRA_TVEC_USER; \ /* test whether the test came from pass/fail */ \ @@ -163,14 +149,9 @@ tvec_hypervisor: \ EXTRA_TVEC_HYPERVISOR; \ /* renting some space out here */ \ other_exception: \ - csrr t6, mepc; \ - la t5, test_fpu_presence; \ - beqz t5, 1f; \ - bne t5, t6, 1f; \ - RVTEST_PASS; \ 1: ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \ write_tohost: \ - csrw tohost, TESTNUM; \ + csrw mtohost, TESTNUM; \ j write_tohost; \ .align 6; \ tvec_machine: \ @@ -185,7 +166,7 @@ tvec_machine: \ .globl _start; \ _start: \ RISCV_MULTICORE_DISABLE; \ - RVTEST_64_ENABLE; \ + CHECK_XLEN; \ la t0, stvec_handler; \ beqz t0, skip_set_stvec; \ csrw stvec, t0; \ @@ -197,7 +178,7 @@ _start: \ EXTRA_INIT_TIMER; \ la t0, 1f; \ csrw mepc, t0; \ - csrr a0, hartid; \ + csrr a0, mhartid; \ eret; \ 1: |