From e0010519c57a2b88d0d03d38c21ba0a68f81f2e2 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Tue, 3 May 2016 11:13:36 -0700
Subject: Fix multicore VM tests

- give harts distinct stacks
- correct the address range used by coherence_torture
---
 v/entry.S | 5 ++++-
 v/vm.c    | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'v')

diff --git a/v/entry.S b/v/entry.S
index 460428a..e4f1ca4 100644
--- a/v/entry.S
+++ b/v/entry.S
@@ -10,7 +10,7 @@
 # define REGBYTES 4
 #endif
 
-#define STACK_TOP (_end + 131072)
+#define STACK_TOP (_end + 4096)
 
   .section ".text.init","ax",@progbits
 
@@ -28,6 +28,9 @@ handle_reset:
   la t0, trap_vector
   csrw mtvec, t0
   la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
+  csrr t0, mhartid
+  slli t0, t0, 12
+  add sp, sp, t0
   csrw mscratch, sp
   li a1, 1337
   la a0, userstart
diff --git a/v/vm.c b/v/vm.c
index 5fd1b11..9fc2ea4 100644
--- a/v/vm.c
+++ b/v/vm.c
@@ -175,7 +175,7 @@ static void coherence_torture()
   // cause coherence misses without affecting program semantics
   uint64_t random = ENTROPY;
   while (1) {
-    uintptr_t paddr = (random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4;
+    uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
 #ifdef __riscv_atomic
     if (random & 1) // perform a no-op write
       asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr));
-- 
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