diff options
| -rw-r--r-- | encoding.h | 2 | ||||
| -rw-r--r-- | p/riscv_test.h | 3 | ||||
| -rw-r--r-- | v/riscv_test.h | 4 |
3 files changed, 7 insertions, 2 deletions
@@ -1567,6 +1567,7 @@ #define CSR_VSTART 0x8 #define CSR_VXSAT 0x9 #define CSR_VXRM 0xa +#define CSR_VCSR 0xf #define CSR_USCRATCH 0x40 #define CSR_UEPC 0x41 #define CSR_UCAUSE 0x42 @@ -2518,6 +2519,7 @@ DECLARE_CSR(utvec, CSR_UTVEC) DECLARE_CSR(vstart, CSR_VSTART) DECLARE_CSR(vxsat, CSR_VXSAT) DECLARE_CSR(vxrm, CSR_VXRM) +DECLARE_CSR(vcsr, CSR_VCSR) DECLARE_CSR(uscratch, CSR_USCRATCH) DECLARE_CSR(uepc, CSR_UEPC) DECLARE_CSR(ucause, CSR_UCAUSE) diff --git a/p/riscv_test.h b/p/riscv_test.h index 2b9aad3..88ca6c1 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -142,7 +142,8 @@ li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ (MSTATUS_FS & (MSTATUS_FS >> 1)); \ csrs mstatus, a0; \ - csrwi fcsr, 0 + csrwi fcsr, 0; \ + csrwi vcsr, 0; #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ diff --git a/v/riscv_test.h b/v/riscv_test.h index f9b4f66..c74e05d 100644 --- a/v/riscv_test.h +++ b/v/riscv_test.h @@ -13,7 +13,9 @@ #define RVTEST_FP_ENABLE fssr x0 #undef RVTEST_VECTOR_ENABLE -#define RVTEST_VECTOR_ENABLE fssr x0 +#define RVTEST_VECTOR_ENABLE \ + csrwi fcsr, 0; \ + csrwi vcsr, 0; #undef RVTEST_CODE_BEGIN #define RVTEST_CODE_BEGIN \ |