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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-03-03 21:16:05 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2014-03-03 21:16:05 -0800 |
| commit | 937aa638de2e6f46253fe56048450430f9ad3942 (patch) | |
| tree | 34c5f176a08fab8587e4acda6ea34ac8e9c17e5f | |
| parent | e6a52cba949ef4943f696a1fc93a620477177874 (diff) | |
| download | env-937aa638de2e6f46253fe56048450430f9ad3942.zip env-937aa638de2e6f46253fe56048450430f9ad3942.tar.gz env-937aa638de2e6f46253fe56048450430f9ad3942.tar.bz2 | |
need to modify status register *before* enabling interrupts
| -rw-r--r-- | p/riscv_test.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index ccf5860..dd5c1b8 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -76,8 +76,8 @@ csrr a0, hartid; \ 1: bnez a0, 1b; \ -#define EXTRA_INIT_TIMER #define EXTRA_INIT +#define EXTRA_INIT_TIMER #define RVTEST_CODE_BEGIN \ .text; \ @@ -86,8 +86,8 @@ _start: \ RISCV_MULTICORE_DISABLE; \ init; \ - EXTRA_INIT_TIMER; \ EXTRA_INIT; \ + EXTRA_INIT_TIMER; \ //----------------------------------------------------------------------- // End Macro |