From 937aa638de2e6f46253fe56048450430f9ad3942 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Mon, 3 Mar 2014 21:16:05 -0800 Subject: need to modify status register *before* enabling interrupts --- p/riscv_test.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/p/riscv_test.h b/p/riscv_test.h index ccf5860..dd5c1b8 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -76,8 +76,8 @@ csrr a0, hartid; \ 1: bnez a0, 1b; \ -#define EXTRA_INIT_TIMER #define EXTRA_INIT +#define EXTRA_INIT_TIMER #define RVTEST_CODE_BEGIN \ .text; \ @@ -86,8 +86,8 @@ _start: \ RISCV_MULTICORE_DISABLE; \ init; \ - EXTRA_INIT_TIMER; \ EXTRA_INIT; \ + EXTRA_INIT_TIMER; \ //----------------------------------------------------------------------- // End Macro -- cgit v1.1