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rocket-tools/riscv-tests/env.git
master
priv-1.10
priv-1.9
riscv-test-env-sail
vectorless
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Commit message
Author
Age
master
Support setting V-env LFSR bits with a compiler flag (#43)
Jerry Zhao
13 months
priv-1.10
Fix physical load address for recent binutils
Andrew Waterman
7 years
priv-1.9
Support RV32 virtual memory tests
Andrew Waterman
8 years
riscv-test-env-sail
created a branch for the sail-riscv testing env
William McSpaddden
3 months
vectorless
disable vector trap handling
Howard Mao
9 years
Age
Commit message
Author
Files
Lines
2023-08-22
Support setting V-env LFSR bits with a compiler flag (#43)
HEAD
master
Jerry Zhao
1
-2
/
+6
2023-03-16
Cope with presence of Smrnmi extension
Andrew Waterman
2
-0
/
+10
2023-03-16
Update encoding.h for Smrnmi definitions
Andrew Waterman
1
-1911
/
+4092
2023-03-03
Increase v env stack size
Andrew Waterman
1
-1
/
+1
2023-02-02
env: trap and page fault filter mechanism (#40)
deepak0414
3
-0
/
+27
2022-01-31
Reverse memcpy direction when evicts a page. (#34)
eistar
1
-1
/
+1
2021-09-24
update riscv_arch.h to support QEMU (#31)
liweiwei90
1
-2
/
+3
2021-07-19
Update encoding.h to add new PTE_ macros
Andrew Waterman
1
-0
/
+4
2021-07-18
Fix __clear_cache(0, 0) compilation issue (#30)
Daniel Lustig
1
-1
/
+1
2020-11-23
Merge pull request #27 from bucaps/satp_stval-fixes
Andrew Waterman
3
-5
/
+5
[...]