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- After discussion in riscv/riscv-tests#315, disable this test case, as it
makes implementation assumptions which are not valid with respect to the
specification.
- Leave code present but commented out.
On branch dev/benm-disable-lrsc-test-4
Changes to be committed:
modified: isa/rv64ua/lrsc.S
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Resolves #303
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https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
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* [rv64ua/lrsc] Initialize memory read out.
Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.
* [rv64ua/lrsc] Use .skip instead of .align.
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Follow-up to b68b39031a730ecc155ed87fba2ed5f111d0ab07.
The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.
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This doesn't reduce coverage for cache-based RV64 systems, but will
improve test runtime and work around the need for smaller test footprint
for scratchpad-based RV32 systems.
I would argue that these microarchitectural tests should be in the
domain of torture, and that the last one should be removed, too.
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- avoid code duplication between RV32 and RV64 variants
- make LR/SC do something interesting on uniprocessors
- avoid requiring M extension
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