| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 1 | -2/+0 |
| 2016-07-22 | Move rv32mi dirty bit test to rv32si | Andrew Waterman | 1 | -0/+1 |
| 2016-03-10 | Add missing rv32mi/rv32si tests | Andrew Waterman | 1 | -0/+1 |
| 2016-03-03 | Some S-mode tests really only belong in M-mode | Andrew Waterman | 1 | -3/+0 |
| 2015-07-05 | New M-mode timers | Andrew Waterman | 1 | -1/+0 |
| 2015-04-03 | Run RV32 tests on spike with --isa=RV32 | Andrew Waterman | 1 | -0/+2 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 1 | -6/+0 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -1/+0 |
| 2014-11-13 | remove zscale specific tests | Yunsup Lee | 1 | -3/+0 |
| 2014-11-12 | beef up rv32si tests | Yunsup Lee | 1 | -0/+10 |
| 2014-01-31 | Add rv32si tests, including illegality of shamt[5] | Andrew Waterman | 1 | -0/+15 |
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index : rocket-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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