| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2022-12-07 | zicntr: separate cycle/instret accessibility test (#439) | Chih-Min Chao | 1 | -2/+3 |
| 2022-06-09 | Test misaligned stores. (#397) | Tim Newsome | 1 | -0/+2 |
| 2022-06-07 | Test misaligned loads. | Tim Newsome | 1 | -0/+2 |
| 2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 1 | -2/+0 |
| 2017-04-07 | Remove defunct IPI tests | Andrew Waterman | 1 | -3/+0 |
| 2016-07-29 | Add RV32 RVC and breakpoint tests | Andrew Waterman | 1 | -1/+2 |
| 2016-07-22 | Move rv32mi dirty bit test to rv32si | Andrew Waterman | 1 | -1/+0 |
| 2016-07-07 | Update WFI test for priv v1.9 | Andrew Waterman | 1 | -1/+0 |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -3/+1 |
| 2016-03-10 | Add missing rv32mi/rv32si tests | Andrew Waterman | 1 | -0/+3 |
| 2016-03-03 | Some S-mode tests really only belong in M-mode | Andrew Waterman | 1 | -0/+1 |
| 2015-04-03 | Run RV32 tests on spike with --isa=RV32 | Andrew Waterman | 1 | -0/+2 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 1 | -0/+18 |
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index : rocket-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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