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path: root/debug/targets/RISC-V/spike32.py
AgeCommit message (Expand)AuthorFilesLines
2024-05-01[debug tests] increase remotetimeout for all spike-based targets (#553)Anatoly Parshintsev1-1/+1
2023-07-17debug: Add support_unavailable_control property.Tim Newsome1-0/+1
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome1-1/+1
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome1-4/+0
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome1-1/+2
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome1-1/+2
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome1-0/+1
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+1
2020-02-14Add tests for vector register access (#244)Tim Newsome1-3/+5
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome1-1/+4
2019-05-16Cover with/without halt groups. (#191)Tim Newsome1-1/+1
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome1-1/+2
2018-12-31Add testing of run-test/idle cases.Tim Newsome1-1/+1
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+1
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome1-1/+2
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-1/+1
2017-09-19Allow multiple reset vectors.Tim Newsome1-1/+1
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28Increase remotetimeout for spike targets.Tim Newsome1-0/+1
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-1/+6
2017-06-26Move target definition into individual files.Tim Newsome1-0/+12