rocket-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2024-07-30	debug: update lds to merge more section (#573)	Mark Zhuang	1	-3/+6
	merge .bss.* to .bss then entry.S can clear it.
2022-10-21	Change memory address used in debug tests. (#422)	Tim Newsome	1	-1/+1
	https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests.
2017-08-28	WIP multicore testing.	Tim Newsome	1	-0/+2

2017-06-26	Move target definition into individual files.	Tim Newsome	1	-0/+36
	Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.