| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
https://github.com/riscv-collab/riscv-openocd/pull/1111 introduces a
change in OpenOCD behavior: a manual trigger should be manually removed
to step/resume from it.
This was not concidered in previous stop-gap solutions
(76ff703d9161945354e334afa45c5dfe7680da60 and
8cc4918e904ca009cd85350fadf6f44e91eca13c)
This commit:
1. Determines if `reserve trigger` is supported by the target.
This can be removed once
https://github.com/riscv-collab/riscv-openocd/pull/1111 is merged.
2. Marks `HwbpManual` test as not applicable in case `reserve trigger`
is not supported.
3. Accounts for the change in OpenOCD's behavior when stepping from a
manual BP.
4. Cleans up some minor mistakes in `HwbpManual`
|
|
Syntax of the command was changed: (on/off) became compulsory.
|
|
[debug] Reserve the trigger in `HwbpManual`
|
|
There is already a mechanism for the test target to supply a known-bad
address, so use that address if it is provided.
|
|
After https://github.com/riscv-collab/riscv-openocd/pull/1111 is merged,
the registers a user wishes to have direct control of should be
reserved.
This is the case in `HwbpManual`.
The test still works with older OpenOCD versions, since no exception
is generated when a command (`riscv reserve_trigger` in this case)
is not found.
|
|
testlib.py:run_all_tests()
|
|
https://github.com/riscv-software-src/riscv-tests/pull/531#issuecomment-2151081139
|
|
HwbpManual test was broken:
* Value read back from `tselect` was compared with `tdata1` value.
https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/gdbserver.py#L701-L703
This resulted in the test being reported as not supported, after all the
triggers were checked.
* `tdata1.type` field was not set to `mcontrol`.
* `tselect` value used to be changed by `handle_reset` and not restored.
https://github.com/riscv-software-src/riscv-tests/blob/408e461da11e0b298c4b69e587729532787212f5/debug/programs/entry.S#L79-L84
* Manual breakpoint used to be left behind.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
|
|
Memory sampling tests fail sporadically for spike targets. A typical
failure looks as follows (ROI from test log):
```
---------------------------------[ Message ]----------------------------------
139670831 not less than 124104544
--------------------------------[ Traceback ]---------------------------------
... SECTION IS SKIPPED FOR READABILITY ...
raise TestFailed(f"{a!r} not less than {b!r}", comment)
testlib.TestFailed
```
Few observations:
- 139670831 is 0x0853352f in hex, while 124104544 is 0x0765af60
- Now, the assert which is failing corresponds to the following
expression:
```
assertLess(value, previous_value + tolerance)
```
- tolerance is `0x500000`. (124104544 - 0x500000) is 0x0715af60
If we look at the sampling output for such failing test, we'll see:
```
...
0x1212340c5c: 0x0715af60
timestamp after: 878087500
timestamp before: 878088133
0x1212340c5c: 0x0853352f
...
```
The log above demonstrates the reason for the failure. Since memory
sampling occures every poll (which by default happens approximately
every 100ms) a value of the counter may exceed the threshold if the time
between subsequent polls is increased (for whatever reason).
In my opinion the failing assert can be safely removed, since the checks
it perform are quite brittle and cannot be generalized. The assert
violation is affected by CPU performance and sporadic delays between
polls.
For now, instead of assert removal we just avoid checks in-between
memory sample bursts. This way we still can be certain that memory
samples are frequent enough and hopefully this will avoid sporadic
failures.
|
|
Remove old warning check in RepeatReadTest
|
|
Check the mcontrol triggers, no other triggers.
|
|
Clear breakpoints so that gdb will not single step
|
|
improvements to debug tests infrastructure to help with triaging process
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Change-Id: Iac914aef8080411e6acd9039c4bdfa728533103c
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Change-Id: I7a4a24972cfa2ddc307a5f06fe3fd5380794719f
|
|
Previously the seed was not printed and this created problems with
reproduction of the issues. It's still not an ideal - meaning
interactions between spike/gdb/openocd are inherently non-determistic
(since time is involved), but at least we should get the same sources
for the same seed now.
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
|
|
This is taking into account that the hardware limits count to 1.
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
|
|
Make the non-existent csr configurable
|
|
Make CLINT address configurable
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
|
|
Test behavior when a hart becomes unavailable while halted.
|
|
Disable timer interrupt to fix some bugs
|
|
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
|
|
This helper uses dmi_write commands to mark harts
available/unavailable.
|
|
|
|
Just doing this to make a change in the debug files, which should now
cause the pylint workflow to execute.
|
|
They have issues when run in a github workflow.
|
|
debug: Test OpenOCD behavior when harts become unavailable, using new spike mechanism
|
|
Use new spike mechanism to test OpenOCD behavior when a hart becomes
unavailable, and then available again.
|
|
Use new spike mechanism to test OpenOCD behavior when the current hart
becomes unavailable while running.
Create ThreadTerminated exception.
|
|
Use the new spike mechanism to test OpenOCD behavior when a hart becomes
unavailable while running.
Create CommandException.
|
|
|
|
|
|
|
|
flushregs is deprecated.
|
|
change warning check in RepeatReadTest
|
|
|
|
|
|
To make sure the rtos module of OpenOCD works well.
Signed-off-by: Chao Du <duchao@eswincomputing.com>
|
|
- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no
samples are collected
- Replace general "Exception" with "TargetsException" in targets.py for XLEN
mismatch
- Introduce "TestLibError" exception in testlib.py and replace general
exceptions in various locations
- Update pylint.rc to remove overgeneral-exceptions warning
|
|
Don't build with -DMULTICORE because this is not a test that really does
multicore. It's one where we just want to park the other harts.
|
|
|
|
Need to set the etrigger on the hart we're running the test against.
|
|
|
|
|
|
Test that we work correctly when the hart we're debugging ceases to
respond while it's running.
|
|
Test that we work correctly when the hart we're debugging ceases to
respond during stepi.
Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete.
Parse "could not read registers" error from gdb
|
|
Confirm basic debug still works when other harts have been parked using
a `cease` instruction. Check that the unavailable harts are inaccessible
from gdb.
Add Gdb.expect()
Parse "unknown thread" error from gdb.
|
