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* WIP
* WIP
* Vector test seems to work well with spike.
* Check a0 in case the program didn't work right.
* Return not applicable if compile doesn't support V
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* Add a basic semihosting test.
* Need to configure semihosting on each target.
* WIP
* Parse "cannot insert breakpoint" message.
Also use sys.exit instead of exit, per new pylint's suggestion.
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Also use sys.exit instead of exit, per new pylint's suggestion.
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bus/hardware device (#274)
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Test the behavior described in
https://github.com/riscv/riscv-openocd/issues/76.
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This isn't appropriate for regression-testing the debug infrastructure,
but is useful as a quick sanity check for unrelated CI runs, where we're
just trying to make sure integration isn't totally borked.
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* Improve address translation tests.
Check that the mode we're testing is supported by hardware before
running the test.
Test with high address bits set, which catches a bug in OpenOCD.
* Turn off PMP for address translation test.
Otherwise it doesn't pass on HiFive Unleashed.
* Run TranslateTest on random hart.
Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
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Otherwise it only passes intermittently when I change _start, which is
very confusing.
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Co-authored-by: WRR <-@->
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This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
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This saves a few seconds every time I run any test.
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This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c.
Resolves #256
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variable DRAM_BASE (#255)
* setup a multilevel page table to avoid misaligned superpages
* Revert "setup a multilevel page table to avoid misaligned superpages"
This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5.
* statically fail if DRAM_BASE is not superpage-aligned
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* Bump riscv-test-env
* Merge master
* Don't assume that mscratch is initialized to a particular value on reset
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Also fix bug in parsing nan.
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3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because
of the value of TESTNUM at the point an expected exception was taken. Fix
by moving the new tests earlier in the program.
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* WIP
* Add vector register smoketest.
Also redo the gdb value parsing code to accommodate the more complicated
way that vector registers look.
* Test vector access a little more thoroughly.
* Revert unnecessary changes.
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This way if you end up reading a value that you suspect might be coming
from another hart/register, you can clearly see where it came from.
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If it's in the path, at least. This way you get human readable assembly
in the log instead of hex values.
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the same size of stack & TLS. (#242)
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overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)
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This catches more corner cases where this may be a problem.
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* WIP
* Smoke test virtual address support.
Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as
large as possible pages to 1:1 map the rest of RAM so those sizes do get
minimal coverage as well.
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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`make` now takes 31s, `make all` takes 1m53s.
The new CheckMisa test ensures that the misa value specified in the
configuration is correct.
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The symbols used to query the size of .tdata and .tbss need not be
thread-local themselves; instead, make them linker script-provided
non-thread-local symbols.
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* Improve parallellism in debug test Makefile
Now each test is an individual make target, so you can get the most out
of however many cores you have. On my 12-core system, `make` went from
2m45s to 42s, and `make all` went from `3m25s` to `2m39s`.
If you have few cores, this change may actually slow things down a bit,
because ExamineTarget is run for every gdbserver.py invocation.
* Remove test target.
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This binary comes from
https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2,
which will hopefully be accepted upstream.
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The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.
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This test checks that an I$ appears to be physically indexed.
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* Parse inf/nan floats.
* Enable mstatus.fs in SimpleF18Test
Also accept "unable to fetch" message when FPRs aren't supported.
* Add config files for HiFive Unleashed.
* Add configs to flash HiFive Unleashed.
All tests pass.
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The latest OpenOCD doesn't need (nor support) this anymore.
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