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| author | Tim Newsome <tim@sifive.com> | 2020-04-10 13:30:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-10 13:30:41 -0700 |
| commit | f2107b6def72e7d7d7eba22712b04c8747547b83 (patch) | |
| tree | d08c50ef898fdea1e6e45975297b0a3975baf1de | |
| parent | 19bfdab48c2a6da4a2c67d5779757da7b073811d (diff) | |
| download | riscv-tests-f2107b6def72e7d7d7eba22712b04c8747547b83.zip riscv-tests-f2107b6def72e7d7d7eba22712b04c8747547b83.tar.gz riscv-tests-f2107b6def72e7d7d7eba22712b04c8747547b83.tar.bz2 | |
Change slen to a value that spike supports. (#271)
| -rw-r--r-- | debug/targets/RISC-V/spike64-2.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py index 5ace23b..5dc0e7b 100644 --- a/debug/targets/RISC-V/spike64-2.py +++ b/debug/targets/RISC-V/spike64-2.py @@ -14,6 +14,8 @@ class spike64_2(targets.Target): support_hasel = False def create(self): + # TODO: It would be nice to test with slen=128, but spike currently + # requires vlen==slen. return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30, support_hasel=False, support_abstract_csr=False, - vlen=512, elen=64) + vlen=512, elen=64, slen=512) |