Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-10-15 | bump env (#298) | Sandeep Rajendran | 1 | -14/+14 | |
2020-10-08 | Expose registers on all harts in openocd cfgs (#297) | Samuel Obuch | 2 | -4/+10 | |
2020-10-02 | Modify PMP benchmark to detect granularity (#295) | Moritz Schneider | 1 | -10/+24 | |
2020-08-31 | Add test for `riscv repeat_read`. (#293) | Tim Newsome | 1 | -0/+34 | |
2020-08-12 | Point people at a compiler that supports vectors. (#290) | Tim Newsome | 1 | -1/+2 | |
Addresses #289. | |||||
2020-08-06 | Add enable_rtos_riscv (#288) | Tim Newsome | 1 | -0/+2 | |
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287. | |||||
2020-07-14 | bump env to fix #286 | Andrew Waterman | 1 | -14/+14 | |
2020-07-01 | Make pylint happy. (#285) | Tim Newsome | 1 | -0/+1 | |
2020-06-25 | Add manual hwbp test. (#283) | Tim Newsome | 4 | -0/+98 | |
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly. | |||||
2020-06-25 | Create a more sophisticated vector test (#284) | Tim Newsome | 4 | -10/+248 | |
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V | |||||
2020-05-26 | Test semihosting calls (#280) | Tim Newsome | 9 | -5/+205 | |
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion. | |||||
2020-05-18 | Parse "cannot insert breakpoint" message. (#279) | Tim Newsome | 1 | -1/+8 | |
Also use sys.exit instead of exit, per new pylint's suggestion. | |||||
2020-05-13 | Update env (#275) | Paul Donahue | 1 | -5/+19 | |
2020-04-17 | The HTIF device must live in its own page since it is (generally) a ↵ | Adrian Harris | 1 | -0/+1 | |
bus/hardware device (#274) | |||||
2020-04-10 | Make TooManyHwbp more thorough. (#272) | Tim Newsome | 1 | -1/+6 | |
Test the behavior described in https://github.com/riscv/riscv-openocd/issues/76. | |||||
2020-04-10 | Change slen to a value that spike supports. (#271) | Tim Newsome | 1 | -1/+3 | |
2020-03-29 | Add debug-check-fast target for | Andrew Waterman | 1 | -0/+4 | |
This isn't appropriate for regression-testing the debug infrastructure, but is useful as a quick sanity check for unrelated CI runs, where we're just trying to make sure integration isn't totally borked. | |||||
2020-03-26 | Improve address translation tests (#261) | Tim Newsome | 4 | -35/+59 | |
* Improve address translation tests. Check that the mode we're testing is supported by hardware before running the test. Test with high address bits set, which catches a bug in OpenOCD. * Turn off PMP for address translation test. Otherwise it doesn't pass on HiFive Unleashed. * Run TranslateTest on random hart. Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work. | |||||
2020-03-26 | Write a NOP program in PrivRw test. (#260) | Tim Newsome | 2 | -9/+8 | |
Otherwise it only passes intermittently when I change _start, which is very confusing. | |||||
2020-03-21 | Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5 | Andrew Waterman | 1 | -7/+7 | |
2020-03-21 | Move self-modifying 'fence.i' ops to .data memory section (#269) | WRansohoff | 1 | -6/+14 | |
Co-authored-by: WRR <-@-> | |||||
2020-03-19 | Fix comments error in fmin.S (#267) | Mohanson | 2 | -4/+4 | |
2020-03-18 | Spike changed --varch syntax (#257) | Tim Newsome | 1 | -2/+2 | |
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417 | |||||
2020-03-18 | Specify misa for HiFive Unleashed. (#259) | Tim Newsome | 1 | -0/+2 | |
This saves a few seconds every time I run any test. | |||||
2020-03-18 | Have both rs=rd and rs!=rd cases in csr.S (#263) | Takahiro | 1 | -12/+15 | |
2020-03-18 | Fix shamt.S header (#264) | Takahiro | 1 | -2/+2 | |
2020-03-16 | Add a test case rs = rd to jalr.S (#258) | Takahiro | 1 | -0/+16 | |
2020-03-11 | Add comment explaining convoluted rv64mi-p-scall behavior | Andrew Waterman | 1 | -0/+6 | |
2020-03-11 | Revert "scall: make the intention of the test in machine mode more clear (#246)" | Andrew Waterman | 1 | -6/+1 | |
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256 | |||||
2020-03-11 | Setup a multilevel page table to avoid misaligned superpages caused by ↵ | Cedric Orban | 1 | -0/+4 | |
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned | |||||
2020-03-06 | Don't assume reset state of mscratch (#254) | Paul Donahue | 2 | -13/+13 | |
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset | |||||
2020-03-05 | bump env (#253) | Han-Kuan Chen | 1 | -12/+12 | |
2020-03-05 | Bump riscv-test-env (#252) | Andrew Waterman | 1 | -5/+17 | |
2020-03-05 | Clean up gdb parsing code. (#247) | Tim Newsome | 1 | -42/+32 | |
Also fix bug in parsing nan. | |||||
2020-03-05 | Add a simple mechanism to skip tests on targets. (#251) | Tim Newsome | 2 | -1/+9 | |
2020-03-02 | enable rv32e compatability by replacing reg x29 with reg x7 (#250) | Cedric Orban | 1 | -12/+12 | |
2020-02-27 | bump env | Andrew Waterman | 1 | -10/+5 | |
2020-02-21 | scall: make the intention of the test in machine mode more clear (#246) | Nils Asmussen | 1 | -1/+6 | |
2020-02-20 | Fix rv64mi-p-csr on systems with FPUs | Andrew Waterman | 1 | -2/+3 | |
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program. | |||||
2020-02-14 | Add tests for vector register access (#244) | Tim Newsome | 5 | -34/+137 | |
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes. | |||||
2020-02-11 | Generate very different values on different harts. (#238) | Tim Newsome | 2 | -4/+5 | |
This way if you end up reading a value that you suspect might be coming from another hart/register, you can clearly see where it came from. | |||||
2020-02-11 | Run OpenOCD output through spike-dasm. (#239) | Tim Newsome | 1 | -3/+9 | |
If it's in the path, at least. This way you get human readable assembly in the log instead of hex values. | |||||
2020-02-11 | Look for \bmain\b instead of ' main '. (#237) | Tim Newsome | 1 | -2/+2 | |
2020-02-08 | Solves https://github.com/riscv/riscv-tests/issues/241 : Each mhartid has ↵ | Sho Nakatani | 1 | -2/+2 | |
the same size of stack & TLS. (#242) | |||||
2020-01-31 | Added CSR test cases on whether writing 0 to CSR works, as that might get ↵ | Torbjørn Viem Ness | 1 | -0/+2 | |
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236) | |||||
2020-01-15 | Force DMI busy in all tests. (#235) | Tim Newsome | 2 | -15/+44 | |
This catches more corner cases where this may be a problem. | |||||
2020-01-09 | Smoke test virtual address translation support. (#233) | Tim Newsome | 6 | -13/+231 | |
* WIP * Smoke test virtual address support. Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as large as possible pages to 1:1 map the rest of RAM so those sizes do get minimal coverage as well. | |||||
2019-12-28 | benchmarks: Disassemble .text.init section (#230) | Albert Ou | 1 | -1/+1 | |
2019-12-24 | submodule: bump env version (#229) | Chih-Min Chao | 1 | -5/+10 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-12-18 | Hardcode misa values for all spike targets. (#227) | Tim Newsome | 9 | -7/+27 | |
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct. |